參數(shù)資料
型號: MACH210A-10VC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High-Density EE CMOS Programmable Logic
中文描述: EE PLD, 10 ns, PQFP44
封裝: TQFP-44
文件頁數(shù): 10/47頁
文件大?。?/td> 347K
代理商: MACH210A-10VC
MACH210A-12/14 (Ind)
18
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tWIGL
Input Latch Gate Width LOW
6
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
17
19.5
ns
tAR
Asynchronous Reset to Registered or Latched Output
19.5
ns
tARW
Asynchronous Reset Width (Note 1)
12
14.5
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
12
10
ns
tAP
Asynchronous Preset to Registered or Latched Output
18
19.5
ns
tAPW
Asynchronous Preset Width (Note 1)
12
14.5
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
12
10
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 3)
12
14.5
ns
tER
Input, I/O, or Feedback to Output Disable (Note 3)
12
14.5
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 16 outputs switching.
-12
-14
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相關代理商/技術參數(shù)
參數(shù)描述
MACH210A-12 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
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MACH210A-14JI 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic