參數(shù)資料
型號: MACH210A-10VC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High-Density EE CMOS Programmable Logic
中文描述: EE PLD, 10 ns, PQFP44
封裝: TQFP-44
文件頁數(shù): 9/47頁
文件大小: 347K
代理商: MACH210A-10VC
17
MACH210A-12/14 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
12
14.5
ns
D-Type
8
8.5
ns
T-Type
9
10
ns
tH
Register Data Hold Time
0
ns
tCO
Clock to Output (Note 3)
7.5
10
ns
tWL
Clock
LOW
6
7.5
ns
tWH
Width
HIGH
6
7.5
ns
D-Type
64
53
MHz
T-Type
59
50
MHz
fMAX
D-Type
80
61.5
MHz
T-Type
72.5
57
MHz
80
66.5
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
8
8.5
ns
tHL
Latch Data Hold Time
0
ns
tGO
Gate to Output (Note 3)
8.5
12
ns
tGWL
Gate Width LOW
6
7.5
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
14.5
17
ns
tSIR
Input Register Setup Time
2.5
ns
tHIR
Input Register Hold Time
3
ns
tICO
Input Register Clock to Combinatorial Output
16
18
ns
tICS
Input Register Clock to Output Register Setup
D-Type
12
14.5
ns
T-Type
13
16
ns
tWICL
Input Register
LOW
6
7.5
ns
tWICH
Clock Width
HIGH
6
7.5
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL + tWICH)
80
66.5
MHz
tSIL
Input Latch Setup Time
2.5
ns
tHIL
Input Latch Hold Time
3
ns
tIGO
Input Latch Gate to Combinatorial Output
17
20.5
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
19.5
23
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
10.5
11
ns
tIGS
Input Latch Gate to Output Latch Setup
13.5
16
ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tS + tH)
-12
-14
tS
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