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參數(shù)資料
| 型號(hào)： | MACH210A-7 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | 高密度電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 39/47頁 |
| 文件大?。?/td> | 347K |
| 代理商： | MACH210A-7 |
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MACH210-7/10/12/15/20, Q-12/15/20
44
POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Max
Unit
tPR
Power-Up Reset Time
10
s
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See
Switching
Characteristics
tPR
tWL
tS
4 V
VCC
Power
Registered
Output
Clock
14128I-26
Power-Up Reset Waveform
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| MACH210A7JC | 制造商:AMD 功能描述:* |
| MACH210A-7JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
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