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參數(shù)資料
| 型號(hào)： | MACH210A-7 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | 高密度電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 46/47頁 |
| 文件大?。?/td> | 347K |
| 代理商： | MACH210A-7 |
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MACH210-7/10/12/15/20, Q-12/15/20
8
The I/O Cell
The I/O cell in the MACH210 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
PCI Compliance
The MACH210A-7/10 is fully compliant with the
PCI
Local Bus Specification published by the PCI Special
Interest Group. The MACH210A-7/10’s predictable
timing ensures compliance with the PCI AC specifica-
tions independent of the design. On the other hand, in
CPLD and FPGA architectures without predictable
timing, PCI compliance is dependent upon routing and
product term distribution.
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| MACH210A7JC | 制造商:AMD 功能描述:* |
| MACH210A-7JC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
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