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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX038CPP+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 12/17闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC GEN WAVEFORM HI-FREQ 20-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 18 |
| 闋荤巼锛� | 0.1Hz ~ 20MHz |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 闆绘祦 - 闆绘簮锛� | 45mA |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-PDIP |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�鐣�(d膩ng)鍓嶇12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�
High-Frequency Waveform Generator
Typical Operating Characteristics
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k
惟/, CL = 20pF, TA = +25掳C, unless
otherwise noted.)
0.1
1
100
1000
OUTPUT FREQUENCY
vs. IIN CURRENT
10
100
MAX038-08
IIN CURRENT (
渭A)
OUTPUT
FREQUENCY
(Hz)
10
1
1k
10k
100k
1M
10M
100M
100
渭F
47
渭F
10
渭F
3.3
渭F
1
渭F
100nF
33nF
3.3nF
330pF
100pF
33pF
1.0
0
-3
2
NORMALIZED OUTPUT FREQUENCY
vs. FADJ VOLTAGE
0.2
0.8
MAX038-09
VFADJ (V)
F
OUT
NORMALIZED
0
0.4
-2
-1
1
0.6
3
1.2
1.4
1.6
1.8
2.0
IIN = 100
渭A, COSC = 1000pF
0.85
NORMALIZED OUTPUT FREQUENCY
vs. DADJ VOLTAGE
0.90
1.10
MAX038-17
DADJ (V)
NORMALIZED
OUTPUT
FREQUENCY 1.00
0.95
1.05
IIN = 10
渭A
IIN = 25
渭A
IIN = 50
渭A
IIN = 100
渭A
IIN = 250
渭A
IIN = 500
渭A
2.0
-2.5
-2.0
-1.0
1.0
2.5
DUTY-CYCLE LINEARITY
vs. DADJ VOLTAGE
-2.0
1.0
MAX038-18
DADJ (V)
DUTY-CYCLE
LINEARITY
ERROR
(%)
0
1.5
0
-1.0
-1.5
-0.5
0.5
1.5
IIN = 10
渭A
IIN = 25
渭A
IIN = 50
渭A
IIN = 100
渭A
IIN = 250
渭A
IIN = 500
渭A
60
0
-3
2
DUTY CYCLE vs. DADJ VOLTAGE
10
50
MAX038-16B
DADJ (V)
DUTY
CYCLE
(%)
0
30
20
-2
-1
1
40
70
80
90
100
3
IIN = 200
渭A
MAX038
4
Maxim Integrated
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX038CPP+ | 鍔熻兘鎻忚堪:IC GEN WAVEFORM HI-FREQ 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷�(j矛)鏅� - 鍙法绋嬭▓(j矛)鏅傚櫒鍜屾尟钑╁櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:45 绯诲垪:- 椤炲瀷:婧害 - 瑁�(b菙)鍎熸櫠楂旀尟钑╁櫒锛圱CXO锛� 瑷�(j矛)鏁�(sh霉):- 闋荤巼:25MHz 闆绘簮闆诲:3.135 V ~ 3.465 V 闆绘祦 - 闆绘簮:1.5mA 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:16-SOIC锛�0.295"锛�7.50mm 瀵級 鍖呰:绠′欢 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SOIC W 瀹夎椤炲瀷:琛ㄩ潰璨艰 |
| MAX038CWP | 鍔熻兘鎻忚堪:IC GEN WAVEFORM HI-FREQ 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅傞悩/瑷�(j矛)鏅� - 鍙法绋嬭▓(j矛)鏅傚櫒鍜屾尟钑╁櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:45 绯诲垪:- 椤炲瀷:婧害 - 瑁�(b菙)鍎熸櫠楂旀尟钑╁櫒锛圱CXO锛� 瑷�(j矛)鏁�(sh霉):- 闋荤巼:25MHz 闆绘簮闆诲:3.135 V ~ 3.465 V 闆绘祦 - 闆绘簮:1.5mA 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:16-SOIC锛�0.295"锛�7.50mm 瀵級 鍖呰:绠′欢 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SOIC W 瀹夎椤炲瀷:琛ㄩ潰璨艰 |
| MAX038CWP+ | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
| MAX038CWP+T | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
| MAX038CWP-T | 鍔熻兘鎻忚堪:鏅傞悩鐧�(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56 |
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