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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MAX038CPP+
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 15/17闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC GEN WAVEFORM HI-FREQ 20-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 18
闋荤巼锛� 0.1Hz ~ 20MHz
闆绘簮闆诲锛� 4.75 V ~ 5.25 V
闆绘祦 - 闆绘簮锛� 45mA
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 20-DIP锛�0.300"锛�7.62mm锛�
鍖呰锛� 绠′欢
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-PDIP
瀹夎椤炲瀷锛� 閫氬瓟
High-Frequency Waveform Generator
0
-100
0
20
60
100
OUTPUT SPECTRUM, SINE WAVE
(Fo = 11.5MHz)
-80
-20
MAX038-12A
FREQUENCY (MHz)
ATTENUATION
(dB)
40
80
-40
-60
-10
-30
-50
-70
-90
10
30
50
70
90
RIN = 15k惟 (VIN = 2.5V), CF = 20pF,
VDADJ = 40mV, VFADJ = -3V
0
-100
010
30
50
OUTPUT SPECTRUM, SINE WAVE
(Fo = 5.9kHz)
-80
-20
MAX038
12B
FREQUENCY (kHz)
ATTENUATION
(dB)
20
40
-40
-60
-10
-30
-50
-70
-90
5
15253545
RIN = 51k惟 (VIN = 2.5V), CF = 0.01渭F,
VDADJ = 50mV, VFADJ = 0V
Pin Description
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = DV+ = 5V, V- = -5V, VDADJ = VFADJ = VPDI = VPDO = 0V, RL = 1k
惟/, CL = 20pF, TA = +25掳C, unless
otherwise noted.)
PIN
NAME
FUNCTION
1
REF
2.50V bandgap voltage reference output
2, 6, 9,
11, 18
GND
Ground*
3
A0
Waveform selection input; TTL/CMOS compatible
4
A1
Waveform selection input; TTL/CMOS compatible
5
COSC
External capacitor connection
7
DADJ
Duty-cycle adjust input
8
FADJ
Frequency adjust input
10
IIN
Current input for frequency control
12
PDO
Phase detector output. Connect to GND if phase detector is not used.
13
PDI
Phase detector reference clock input. Connect to GND if phase detector is not used.
14
SYNC
TTL/CMOS-compatible output, referenced between DGND and DV+. Permits the internal oscillator to be
synchronized with an external signal. Leave open if unused.
15
DGND
Digital ground
16
DV+
Digital +5V supply input. Can be left open if SYNC is not used.
17
V+
+5V supply input
19
OUT
Sine, square, or triangle output
20
V-
-5V supply input
*The five GND pins are not internally connected. Connect all five GND pins to a quiet ground close to the device. A ground plane is
recommended (see Layout Considerations).
MAX038
Maxim Integrated
7
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
MAX038CPP+ 鍔熻兘鎻忚堪:IC GEN WAVEFORM HI-FREQ 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鍙法绋嬭▓(j矛)鏅�(sh铆)鍣ㄥ拰鎸暕鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:45 绯诲垪:- 椤炲瀷:婧害 - 瑁�(b菙)鍎熸櫠楂旀尟钑╁櫒锛圱CXO锛� 瑷�(j矛)鏁�(sh霉):- 闋荤巼:25MHz 闆绘簮闆诲:3.135 V ~ 3.465 V 闆绘祦 - 闆绘簮:1.5mA 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:16-SOIC锛�0.295"锛�7.50mm 瀵級 鍖呰:绠′欢 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SOIC W 瀹夎椤炲瀷:琛ㄩ潰璨艰
MAX038CWP 鍔熻兘鎻忚堪:IC GEN WAVEFORM HI-FREQ 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鍙法绋嬭▓(j矛)鏅�(sh铆)鍣ㄥ拰鎸暕鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:45 绯诲垪:- 椤炲瀷:婧害 - 瑁�(b菙)鍎熸櫠楂旀尟钑╁櫒锛圱CXO锛� 瑷�(j矛)鏁�(sh霉):- 闋荤巼:25MHz 闆绘簮闆诲:3.135 V ~ 3.465 V 闆绘祦 - 闆绘簮:1.5mA 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:16-SOIC锛�0.295"锛�7.50mm 瀵級 鍖呰:绠′欢 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SOIC W 瀹夎椤炲瀷:琛ㄩ潰璨艰
MAX038CWP+ 鍔熻兘鎻忚堪:鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
MAX038CWP+T 鍔熻兘鎻忚堪:鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
MAX038CWP-T 鍔熻兘鎻忚堪:鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56