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參數(shù)資料
| 型號： | MAX038CPP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 0K |
| 描述： | IC GEN WAVEFORM HI-FREQ 20-DIP |
| 標準包裝： | 18 |
| 頻率： | 0.1Hz ~ 20MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 安裝類型： | 通孔 |
PDO is a rectangular current-pulse train, alternating
between 0A and 500A. It has a 50% duty cycle when
the MAX038 output and PDI are in phase-quadrature
(90° out of phase). The duty cycle approaches 100%
as the phase difference approaches 180° and con-
versely, approaches 0% as the phase difference
approaches 0°. The gain of the phase detector (KD)
can be expressed as:
KD = 0.318 x RPD (volts/radian)
[16]
where RPD = phase-detector gain-setting resistor.
When the loop is in lock, the input signals to the phase
detector are in approximate phase quadrature, the duty
cycle is 50%, and the average current at PDO is 250A
(the current sink of FADJ). This current is divided
between FADJ and RPD; 250A always goes into FADJ
and any difference current is developed across RPD,
creating VFADJ (both polarities). For example, as the
phase difference increases, PDO duty cycle increases,
the average current increases, and the voltage on RPD
(and VFADJ) becomes more positive. This in turn
decreases the oscillator frequency, reducing the phase
difference, thus maintaining phase lock. The higher
RPD is, the greater VFADJ is for a given phase differ-
ence; in other words, the greater the loop gain, the less
the capture range. The current from PDO must also
charge CPD, so the rate at which VFADJ changes (the
loop bandwidth) is inversely proportional to CPD.
The phase error (deviation from phase quadrature)
depends on the open-loop gain of the PLL and the ini-
tial frequency deviation of the oscillator from the exter-
nal signal source. The oscillator conversion gain (Ko) is:
KO =
Δωo ÷ ΔVFADJ
[17]
which, from equation [6] is:
KO = 0.2915 x
ωo (radians/sec)
[18]
The loop gain of the PLL system (KV) is:
KV= KD x KO
[19]
where:
KD = detector gain
KO = oscillator gain.
With a loop filter having a response F(s), the open-loop
transfer function, T(s), is:
T(s) = KD x KO x F(s) ÷ s
[20]
Using linear feedback analysis techniques, the closed-
loop transfer characteristic, H(s), can be related to the
open-loop transfer function as follows:
H(s) = T(s) ÷ [1+ T(s)]
[21]
The transient performance and the frequency response
of the PLL depends on the choice of the filter charac-
teristic, F(s).
When the MAX038 internal phase detector is not used,
PDI and PDO should be connected to GND.
External Phase Detectors
External phase detectors may be used instead of the
internal phase detector. The external phase detector
shown in Figure 4 duplicates the action of the MAX038’s
internal phase detector, but the optional ÷N circuit can
be placed between the SYNC output and the phase
detector in applications requiring synchronizing to an
exact multiple of the external oscillator. The resistor net-
work consisting of R4, R5, and R6 sets the sync range,
while capacitor C4 sets the capture range. Note that
this type of phase detector (with or without the ÷N cir-
cuit) locks onto harmonics of the external oscillator as
well as the fundamental. With no external oscillator
input, this circuit can be unpredictable, depending on
the state of the external input DC level.
Figure 4 shows a frequency phase detector that locks
onto only the fundamental of the external oscillator.
With no external oscillator input, the output of the fre-
quency phase detector is a positive DC voltage, and
the oscillations are at the lowest frequency as set by
R4, R5, and R6.
High-Frequency Waveform Generator
MAX038
GND
COSC
12
A0
V-
18
11
9
26
GND GND
15
DGND
GND GND
5
8
10
7
1
13
3
FADJ
IIN
DADJ
REF
RD
OUT
PDI
PDO
V+
17
DV+
16
20
+5V -5V
C1
1
μF
C2
1
μF
CENTER
FREQUENCY
50
Ω
ROUT
CF
RPD
CPD
19
RF
OUTPUT
A1
4
SYNC
14
EXTERNAL OSC INPUT
Figure 3. Phase-Locked Loop Using Internal Phase Detector
MAX038
Maxim Integrated
13
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| MAX038CPP+ | 功能描述:IC GEN WAVEFORM HI-FREQ 20-DIP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 可編程計時器和振蕩器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:45 系列:- 類型:溫度 - 補償晶體振蕩器（TCXO） 計數(shù):- 頻率:25MHz 電源電壓:3.135 V ~ 3.465 V 電流 - 電源:1.5mA 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 包裝:管件 供應(yīng)商設(shè)備封裝:16-SOIC W 安裝類型:表面貼裝 |
| MAX038CWP | 功能描述:IC GEN WAVEFORM HI-FREQ 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 可編程計時器和振蕩器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:45 系列:- 類型:溫度 - 補償晶體振蕩器（TCXO） 計數(shù):- 頻率:25MHz 電源電壓:3.135 V ~ 3.465 V 電流 - 電源:1.5mA 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 包裝:管件 供應(yīng)商設(shè)備封裝:16-SOIC W 安裝類型:表面貼裝 |
| MAX038CWP+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX038CWP+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX038CWP-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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