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參數(shù)資料
| 型號： | MAX11040GUU+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 26/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 4CH 38-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 50 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 64k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 108mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 38-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
| 配用： | MAXSPCSPARTAN6+-ND - ADC and DAC Eval Expansion Board |
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MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
32
Maxim Integrated
Source Impedance and
Input Sampling Network
The source impedance that drives the analog inputs
affects the sampling period.
Low-Impedance Sources
Minimize the source impedance to ensure the input
capacitor fully charges during the sampling phase.
The required source resistance is defined by the
equation below:
where K = 1.5 and RINT = 2600
Ω.
For example, the required source resistance to achieve
0.1% accuracy is:
High-Impedance Sources
If
the
source
impedance
is
greater
than
RSOURCE_MAX, as defined in the Low-Impedance
Sources section, place a 0.1μF bypass capacitor
between AIN_+ and AIN_- to provide transient charge.
The average switched-capacitor load with a proper
bypass capacitor and XIN clock frequency =
24.576MHz is equivalent to a 130k
Ω resistor connect-
ed between AIN_+ and AIN_-. This resistance is inde-
pendent of the value of the 0.1μF bypass capacitor. If
another XIN clock frequency is chosen, this resistance
is directly proportional to the XIN clock period.
Although the addition of a bypass capacitor helps charge
the devices’ 0 input capacitor, some gain error due to
resistive drop across the source resistance still remains.
Calculate this gain error using the following equation:
Analog Filtering
The analog filtering requirements in front of the devices
are considerably reduced compared to a conventional
converter with no on-chip filtering. The internal digital
filter has significant rejection of signals higher than the
Nyquist frequency of the output data rate that would
alias back into the sampled signal.
The internal digital filter does not provide rejection
close to the harmonics of the 3.072MHz modulator fre-
quency. For example, assuming an output data rate of
16ksps if the XIN clock is set to 24.576MHz, then the
band between 3.0686MHz and 3.0750MHz is not
explicitly filtered. Since this unfiltered band is very
small compared to its actual frequency, very little
broadband noise enters through this mechanism. If
focused narrowband noise in this band is present, a
simple analog filter can create significant attenuation at
this frequency because the ratio of passband-to-stop-
band frequency is large.
In addition, because the device’s common-mode rejec-
tion extends out to several 100kHz, the common-mode
noise susceptibility in this frequency range is substan-
tially reduced.
Providing additional filtering in some applications
ensures that differential noise signals outside the fre-
quency band of interest do not saturate the analog
modulator.
The modulator saturates if the input voltage exceeds its
full scale (±2.2V). The digital filter does not prevent a
large signal in the filter stopband from saturating the
modulator. If signals outside the band of interest cause
violation of this full scale while accurate conversion of
passband signals is desired, then additional analog fil-
tering is required to prevent saturation.
Compensating for the Rolloff of
the Digital Filter in Typical FFT Analysis
To calculate FIR_GAIN(fAIN_):
1) Decide the number of evenly spaced frequencies
between DC and the Nyquist frequency of the output
data rate at which correction factors are desired,
which is usually the same as the FFT result.
2) Create an array with a length that is 2x the number of
the desired frequencies. (Again, the result is likely to
correlate with the time domain array that is loaded
into an FFT algorithm.)
3) Fill this array with the filter coefficients provided in
the
Digital Filter section. Fill the rest of the array with
zeros.
4) Take an FFT of this array. The result represents the
response of the devices’ built-in FIR filter.
Δ
Ω
Gain
R
RR
R
Rk
SOURCE
LOAD
SOURCE
=
+
=
+ 130
R
ns
xpF x
ns
xpF x
ns
xpF x
SOURCE MAX
_
.
ln
.%
.
ln
.
<
=
()
==
120
15
4
1
01
2600
120
1 5
4
1000
2600
120
15
4
691
2600
294
Ω
ΩΩ
R
t
Kx C
x In
Error
R
ns
xpF x In
Error
SOURCE MAX
SAMP
INT
_
.
<
=
1
120
15
4
1
2600
Ω
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11040GUU/GH9 | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX11040GUU+ | 功能描述:模數(shù)轉換器 - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11040GUU+T | 功能描述:模數(shù)轉換器 - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11040K | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040K_1111 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
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