參數(shù)資料
型號: MAX1116EKA+T
廠商: Maxim Integrated Products
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC ADC 8BIT SERIAL SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 100k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 910µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個單端,單極
產(chǎn)品目錄頁面: 1395 (CN2011-ZH PDF)
其它名稱: MAX1116EKA+TDKR
MAX1115/MAX1116
Digital Inputs and Outputs
The MAX1115/MAX1116 perform conversions by using
an internal clock. This frees the P from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the P’s convenience
at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
be brought high for at least 50ns, then brought low to
initiate a conversion. To select VDD/2 for conversion,
the CNVST pin must be brought high and low for a
second time (Figures 6c and 6d).
Single-Supply, Low-Power, Serial 8-Bit ADCs
8
_______________________________________________________________________________________
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE LOW
CH0
tCSH
tCONV
tcp
tccs
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE HIGH
CH0
tCSH
tCONV
tcp
tccs
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High
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