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參數(shù)資料
| 型號： | MAX1116EKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SERIAL SOT23-8 |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 910µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1395 (CN2011-ZH PDF) |
| 其它名稱： | MAX1116EKA+TDKR |
MAX1115/MAX1116
Detailed Description
The MAX1115/MAX1116 ADCs use a successive-
approximation conversion technique and input
track/hold (T/H) circuitry to convert an analog signal to
an 8-bit digital output. The SPI/QSPI/MICROWIRE-
compatible interface directly connects to microproces-
sors (Ps) without additional circuitry (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in the
equivalent-input circuit shown in Figure 4 and is com-
posed of the T/H, input multiplexer, input comparator,
switched capacitor DAC, and auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog input
(CH0) is connected to the hold capacitor (CHOLD).
Once the acquisition is complete, the T/H switch opens
and CHOLD is connected to GND, which retains the
charge on CHOLD as a sample of the signal at the ana-
log input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of <1.5k
is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs also improves the accuracy
of an input sample.
Conversion Process
The MAX1115/MAX1116 conversion process is internal-
ly timed. The total acquisition and conversion process
takes <7.5s. Once an input sample has been
acquired, the comparator’s negative input is then con-
nected to an auto-zero supply. Since the device
requires only a single supply, the negative input of the
comparator is set to equal VDD/2. The capacitive DAC
restores the positive input to VDD/2 within the limits of 8-
bit resolution. This action is equivalent to transferring a
charge QIN = 16pF VIN from CHOLD to the binary-
weighted capacitive DAC, which forms a digital repre-
sentation of the analog-input signal.
Single-Supply, Low-Power, Serial 8-Bit ADCs
6
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1VDD
Positive Supply Voltage
2
CH0
Analog Voltage Input
3, 5
I.C.
Internally Connected. Connect to ground.
4
GND
Ground
6
CNVST
Convert/Start Input. CNVST initiates a power-up and starts a conversion on its falling edge.
7
DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance
once data has been fully clocked out.
8
SCLK
Serial Clock. Used for clocking out data on DOUT.
VDD
3k
CLOAD
GND
DOUT
CLOAD
GND
3k
DOUT
a) VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
VDD
3k
CLOAD
GND
DOUT
CLOAD
GND
3k
DOUT
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1117 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs |
| MAX1117EKA | 制造商:Maxim Integrated Products 功能描述:8 PIN COUNT SOT PACKAGE TYPE (MARK:AADW - Cut Tape Product |
| MAX1117EKA+ | 制造商:Maxim Integrated Products 功能描述:ADC SGL SAR 100KSPS 8BIT SERL 8PIN SOT-23 - Rail/Tube |
| MAX1117EKA+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2Ch Single-Supply Low Pwr Serial 8-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1117EKA+TW | 制造商:Maxim Integrated Products 功能描述:+2.7V TO +3.6V, SINGLE-SUPPLY, LOW-POWER, 2-C - Tape and Reel |
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