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參數(shù)資料
| 型號： | MAX1124EGK+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT LVDS/PAR 68QFN-EP |
| 標準包裝： | 30 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | LVDS，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 657mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極 |
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
8
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
AVCC
Analog Supply Voltage. Bypass each pin with a 0.1F capacitor for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
AGND
Analog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.
3
REFIO
Reference Input/Output. With REFADJ pulled high through a 1k
Ω resistor, this I/O port allows
an external reference source to be connected to the MAX1124. With REFADJ pulled low
through the same 1k
Ω resistor, the internal 1.23V bandgap reference is active.
4
REFADJ
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AVCC through a 1k
Ω resistor, the
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1k
Ω resistor, the internal reference is used to determine the
full-scale range of the data converter.
8
INP
Positive Analog Input Terminal
9
INN
Negative Analog Input Terminal
17
CLKDIV
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
22
CLKP
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
23
CLKN
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
50
58
57
59
55
54
56
52
51
53
60
30
48
54
36
42
60
66
72
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.8148MHz,
fSAMPLE = 249.856MHz, AIN = -0.5dBFS)
MAX1124
toc27
CLOCK DUTY CYCLE (%)
SINAD
(dB)
-100
-80
-90
-60
-70
-50
-40
5
101520253035
NOISE POWER RATIO PLOT
MAX1124
toc28
ANALOG INPUT FREQUENCY (MHz)
POWER
SPECTRAL
DENSITY
(dB)
fSAMPLE = 250MHz
fNOTCH = 28.8MHz
NPR = 54.8dB
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, VAGND = VOGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
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