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參數資料
| 型號： | MAX1124EGK+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT LVDS/PAR 68QFN-EP |
| 標準包裝： | 30 |
| 位數： | 10 |
| 采樣率（每秒）： | 250M |
| 數據接口： | LVDS，并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 657mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個單端，單極；1 個差分，單極 |
Digital Outputs (D0P/N–D9P/N, DCLKP/N,
ORP/N) and Control Input
T/B
The digital outputs D0P/N–D9P/N, DCLKP/N, and
ORP/N
are
LVDS
compatible,
and
data
on
D0P/N–D9P/N is presented in either binary or two’s
complement format (Table 1). The
T/B control line is an
LVCMOS-compatible input, which allows the user to
select the desired output format. Pulling
T/B low outputs
data in two’s complement and pulling it high presents
data in offset binary format on the 10-bit parallel bus.
T/B has an internal pulldown resistor and may be left
unconnected in applications using only two’s comple-
ment output format. All LVDS outputs provide a typical
voltage swing of 0.4V around a common-mode voltage
of approximately 1.2V, and must be terminated at the
far end of each transmission line pair (true and comple-
mentary) with 100Ω. The LVDS outputs are powered
from a separate power supply, which can be operated
between 1.7V and 1.9V.
The MAX1124 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1124 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an exter-
nal resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or pre-
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________
13
REFERENCE
BUFFER
REFIO
REFADJ
AVCC
AVCC/2
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
ADC FULL-SCALE = REFT - REFB
G
1V
0.1
μF
REFERENCE-
SCALING
AMPLIFIER
REFT
REFB
13k
Ω TO 1MΩ
13k
Ω TO 1MΩ
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
MAX1124
50
Ω
CLKP
CLKN
SINGLE-ENDED
INPUT TERMINAL
MC100LVEL16
510
Ω
510
Ω
150
Ω
150
Ω
VCLK
VGND
2
3
45
6
7
8
0.1
μF
0.1
μF
0.1
μF
0.1
μF
0.01
μF
10
D0P/N–D9P/N
AVCC OVCC
AGND
OGND
INP
INN
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
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| MAX1124EGK-TD | 功能描述:模數轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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