參數(shù)資料
型號: MAX1124EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 7/17頁
文件大?。?/td> 0K
描述: IC ADC 10BIT LVDS/PAR 68QFN-EP
標準包裝: 30
位數(shù): 10
采樣率(每秒): 250M
數(shù)據(jù)接口: LVDS,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 657mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極;1 個差分,單極
of ferrite beads and capacitors to their corresponding
grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47F tantalum capacitor in
parallel with 10F and 1F ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1F ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1124.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX1124 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and opti-
mized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed at
the package bottom surface, facing the PCB side of the
package. This allows a solid attachment of the package
to the PCB with standard infrared (IR) flow soldering
techniques.
Note that thermal efficiency is not the key factor, since
the MAX1124 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PCB’s
analog ground layer.
Considerable care must be taken, when routing the dig-
ital output traces for a high-speed, high-resolution data
converter. It is essential to keep trace lengths at a mini-
mum and place minimal capacitive loading—less than
5pF—on any digital trace to prevent coupling to sensi-
tive analog sections of the ADC. It is recommended to
run the LVDS output traces as differential lines with
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________
15
MAX1124
10
D0P/N–D9P/N
AVCC
OVCC
AGND
OGND
AGND
ANALOG POWER-
SUPPLY SOURCE
DIGITAL/OUTPUT-
DRIVER POWER-
SUPPLY SOURCE
BYPASSING—ADC LEVEL
BYPASSING—BOARD LEVEL
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1
μF CAPACITOR CLOSE TO THE ADC.
1
μF10μF47μF
AVCC
0.1
μF0.1μF
1
μF10μF47μF
OVCC
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1124
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