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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX1254BEUE+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 25/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT W/REF 16-TSSOP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 2,500 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 94k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞夋彌鍣ㄦ暩(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 15mW |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛楋紝闆� ± |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 16-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
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MAX1253/MAX1254
Stand-Alone, 10-Channel, 12-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
_______________________________________________________________________________________
5
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been calibrated.
Note 2: Offset nulled.
Note 3: In reference mode 00, the reference system powers up for each temperature measurement. In reference mode 01, the ref-
erence system powers up once per sequence of channels scanned. If a sample wait <80s is programmed, the reference
system is on all the time. In reference mode 10, the reference system is on all the time (see Table 7).
Note 4: No external capacitor on REF.
Note 5: The operational input voltage range for each individual input of a differentially configured pair (AIN0鈥揂IN7) is from GND to
VDD. The operational input voltage difference is from -VREF/2 to +VREF/2.
Note 6: See Figure 3 and the Sampling Error vs. Input Source Impedance graph in the Typical Operating Characteristics section.
Note 7: Grade A tested at +10掳C and +55掳C. -20掳C to +85掳C and -40掳C to +85掳C specifications guaranteed by design. Grade B
tested at +25掳C. TMIN to TMAX specification guaranteed by design.
Note 8: External temperature measurement mode using an MMBT3904 (Diodes Inc.) as a sensor. External temperature sensing
from -40掳C to +85掳C; MAX1253/MAX1254 held at +25掳C.
Note 9: Performing eight single-ended external channels鈥� temperature measurements, an internal temperature measurement, and
an internal VDD measurement with no sample wait results in a conversion rate of 2ksps per channel.
Note 10: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal VDD measure-
ment with no sample wait results in a conversion rate of 7ksps per channel.
Note 11: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal VDD measure-
ment with maximum sample wait results in a conversion rate of 3ksps per channel.
Note 12: Defined as the shift in the code boundary as a result of supply voltage change. VDD = min to max; full-scale input, mea-
sured using external reference.
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1253), VDD = +4.5V to +5.5V (MAX1254), TA = TMIN to TMAX, unless otherwise noted.) (Figures 1, 2, and 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
100
0.5
ns
SCLK Pulse Width High Time
tCH
45
ns
SCLK Pulse Width Low Time
tCL
45
ns
DIN to SCLK Setup Time
tDS
25
ns
DIN to SCLK Hold Time
tDH
0ns
CS Fall to SCLK Rise Setup
tCSS
25
ns
SCLK Rise to CS Rise Hold
tCSH
50
ns
SCLK Fall to DOUT Valid
tDOV
CL = 30pF
50
ns
CS Rise to DOUT Disable
tDOD
CL = 30pF
40
ns
CS Fall to DOUT Enable
tDOE
CL = 30pF
40
ns
CS Pulse Width High
tCSW
40
ns
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