with Internal Temperature Sensor and VDD
參數(shù)資料
型號: MAX1254BEUE+T
廠商: Maxim Integrated Products
文件頁數(shù): 29/29頁
文件大?。?/td> 0K
描述: IC ADC 12BIT W/REF 16-TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 12
采樣率(每秒): 94k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
MAX1253/MAX1254
Stand-Alone, 10-Channel, 12-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
_______________________________________________________________________________________
9
Pin Description
PIN
NAME
FUNCTION
1
AIN0
Analog Voltage Input/Temperature Input Channel 0 or Positive Differential Input Relative to AIN1
2
AIN1
Analog Voltage Input/Temperature Input Channel 1 or Negative Differential Input Relative to AIN0
3
AIN2
Analog Voltage Input/Temperature Input Channel 2 or Positive Differential Input Relative to AIN3
4
AIN3
Analog Voltage Input/Temperature Input Channel 3 or Negative Differential Input Relative to AIN2
5
AIN4
Analog Voltage Input/Temperature Input Channel 4 or Positive Differential Input Relative to AIN5
6
AIN5
Analog Voltage Input/Temperature Input Channel 5 or Negative Differential Input Relative to AIN4
7
AIN6
Analog Voltage Input/Temperature Input Channel 6 or Positive Differential Input Relative to AIN7
8
AIN7
Analog Voltage Input/Temperature Input Channel 7 or Negative Differential Input Relative to AIN6
9
REF
Positive Reference Input in External Mode. Bypass REF with a 0.1F capacitor to GND when in external mode.
When using the internal reference, REF must be left open.
10
INT
Interrupt Output. Push-pull or open drain with selectable polarity. See Table 9 and the INT Interrupt Output section.
11
DOUT
Serial Data Output. DOUT transitions on the falling edge of SCLK. High impedance when CS is at logic high.
12
GND
Ground
13
VDD
Positive Power Supply. Bypass with a 0.1F capacitor to GND.
14
DIN
Serial Data Input. DIN data is latched into the serial interface on the rising edge of the SCLK.
15
SCLK
Serial Clock Input. Clocks data in and out of the serial interface (duty cycle must be 40% to 60%).
16
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high
impedance, and the serial interface resets.
ACCUMULATOR
INTERNAL TEMP
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
VDD/2
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN0
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN1
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN2
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN3
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN4
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN5
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN6
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
ACCUMULATOR
AIN7
UPPER
THRESHOLD
LOWER
THRESHOLD
CHANNEL
CONFIGURATION
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
VDD
MUX
TEMP
SENSOR
REFERENCE
12-BIT
ADC WITH
T/H
SCAN
AND
CONVERSION
CONTROL
POR
POWER-
GOOD
INPUT CHANNEL REGISTER
INPUT CONFIGURATION REGISTER
STEP-UP REGISTER
ALARM REGISTER
AVERAGING
DIGITAL
COMPARATOR
SERIAL
INTERFACE
REF
DOUT
DIN
SCLK
INT
CS
MAX1253
MAX1254
Block Diagram
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