with Internal Temperature Sensor and VDD
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MAX1253/MAX1254
Stand-Alone, 10-Channel, 12-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
14
______________________________________________________________________________________
Clock pulses on SCLK shift data into DIN on the rising
edge of the SCLK and out of DOUT on the falling edge
of SCLK.
Data transfers require a logic low on CS. A high-to-low
transition of CS marks the beginning of a data transfer. A
logic high on CS at any time resets the serial interface.
See Figure 6 and the Timing Characteristics table for
detailed serial-interface timing information.
Input Data Format
Serial communications always begin with an 8-bit com-
mand word, serially loaded from DIN. A high-to-low
transition on CS initiates the data input operation. The
command word and the subsequent data bytes (for
write operations) are clocked from DIN into the
MAX1253/MAX1254 on the rising edges of SCLK. The
first rising edge on SCLK, after CS goes low, clocks in
the MSB of the command word (see the Command
Word section). The next seven rising edges on SCLK
complete the loading of the command word into the
internal command register. After the 8-bit command
word is entered, transfer 0 to 20 bytes of data, depend-
ing on the command. Table 2 shows the number of
data bytes for each command.
Output Data Format
Output data from the MAX1253/MAX1254 is clocked
onto DOUT on the falling edge of SCLK. Single-ended
and unipolar differential measurements are output in
straight binary MSB first, with two 8-bytes-per-conver-
sion result, and the last 4 bits padded with zeros. For
temperature and bipolar differential voltage measure-
ments, the output is two鈥檚 complement binary in the
same 2-byte format. The MSB of the output data from a
read command transitions at DOUT after the falling
edge of the 8th SCLK clock pulse following the CS
high-to-low transition. Table 2 shows the number of
bytes to be read from DOUT for a given read com-
mand.
Command Word
The command word (Table 1) controls all serial com-
munications and configuration of the MAX1253/
MAX1254, providing access to the 44 on-chip registers.
The first 4 MSBs of the command word specify the
command (Table 2), while the last 4 bits provide
address information.
The first rising edge on SCLK, after CS goes low, trans-
fers the command word MSB into DIN. The next seven
rising edges on SCLK shift the remaining 7 bits into the
internal command register (see the Serial Digital
Interface section).
HIGH-Z
tCSS
tDOE
tDS
tDH
tCH
tCL
tCP
tDOV
tDOD
tCSH
tCSW
SCLK
DIN
DOUT
CS
Figure 6. Detailed Serial Interface Timing Diagram
Table 1. Command Word
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0 (LSB)
Command B3
Command B2
Command B1
Command B0
Address B3
Address B2
Address B1
Address B0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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IDT723662L15PF8 IC FIFO BI SYNC 8192X36 120QFP
HIN211ECBZ IC 4DRVR/5RCVR RS232 5V 28-SOIC
VE-2WR-MX-F2 CONVERTER MOD DC/DC 7.5V 75W
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鍙冩暩(sh霉)鎻忚堪
MAX1254EVC16 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC Stand-Alone 10-Channel 12-Bit System Monitors with Internal Temperature Sensor and VDD Monitor RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX1254EVKIT 鍔熻兘鎻忚堪:鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻� IC 闁�(k膩i)鐧�(f膩)宸ュ叿 Evaluation Kit/Evaluation System for the MAX1254 MAX1253 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Demonstration Kits 椤炲瀷:ADC 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADS130E08 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:- 6 V to + 6 V
MAX12553ETL 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:14-BIT, 65MSPS, 3.3V ADC - Bulk
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MAX12553ETL+T 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:ADC SGL PIPELINED 65MSPS 14BIT PARALLEL 40TQFN - Tape and Reel