參數(shù)資料
型號(hào): MAX127ACAI+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 0K
描述: IC DAS 12BIT 2-WIRE 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
類(lèi)型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 12 b
采樣率(每秒): 8k
數(shù)據(jù)接口: I²C,串行
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX;
unless otherwise noted. Typical values are at TA = +25°C.)
Note 1:
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-
Supply Rejection test.
Note 2:
External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.
Note 3:
Ground “on” channel, sine wave applied to all “off” channels.
Note 4:
Guaranteed by design. Not tested.
Note 5:
Use static external load during conversion for specified accuracy.
Note 6:
Tested using internal reference.
Note 7:
PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Note 8:
Not subject to production testing. Provided for design guidance only.
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Low Period of the SCL Clock
tLOW
4.7
s
High Period of the SCL Clock
tHIGH
4.0
s
Setup Time for a Repeated
START Condition
tSU, STA
4.7
s
Data Hold Time
tHD, DAT
0
0.9
s
Data Setup Time
tSU, DAT
250
ns
Rise Time for Both SDA and SCL
Signals (Receiving)
tR
1000
ns
Fall Time for Both SDA and SCL
Signals (Receiving)
tF
300
ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
tF
Cb = total capacitance of one bus line in pF,
up to 6mA sink
20 +
250
0.1 x Cb
ns
Setup Time for STOP Condition
tSU, STO
4.0
s
Capacitive Load for Each
Bus Line
Cb
400
pF
Pulse Width of Spike Suppressed
tSP
0
50
ns
Hold Time (Repeated) START
Condition
tHD,STA
4.0
s
Bus Free Time Between a STOP
and START Condition
tBUF
4.7
s
SCL Clock Frequency
fSCL
100
kHz
2-WIRE STANDARD MODE
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