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參數(shù)資料
| 型號： | MAX1359BETL+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 46/71頁 |
| 文件大小： | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.84k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 管件 |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
50
______________________________________________________________________________________
The SLEEP_CFG register allows users to program spe-
cific behavior for the 32kHz oscillator, buffer, and PWM
in sleep mode. It also contains a sleep-control bit (SLP)
to enable sleep mode.
SLP (ADR0): Sleep bit. The SLP bit is the LSB in the
SLEEP_CFG address control byte. Set SLP = 1 to
assert the SHDN bit and enter sleep mode. Writing the
register with SLP = 0 or reading with SLP = 0 or
SLP = 1 has no effect on the SHDN bit.
SOSCE: Sleep-mode 32kHz crystal oscillator enable
bit. SOSCE = 1 enables the 32kHz oscillator in sleep
mode, and SOSCE = 0 disables it in sleep mode,
regardless of the state of the OSCE bit. The power-on
default is 1.
SCK32E: Sleep-mode CK32K-pin output-buffer enable
bit. SCK32E = 1 enables the 32kHz output buffer in
sleep mode, and SCK32E = 0 disables it in sleep
mode, regardless of the state of the CK32E bit. The
power-on default is 1.
SPWME: Sleep-mode PWM enable bit. SPWME = 1
enables the internal PWM in sleep mode, and
SPWME = 0 disables it in sleep mode, regardless of the
state of the PWME bit.
Input frequencies are limited to 32.768kHz or lower
since the high-frequency clock is disabled in sleep
mode. SOSCE must be asserted to have 32kHz avail-
able as an input to the PWM. The power-on default is 0.
SHDN: Shutdown bit. This bit is read only. SHDN is
asserted by writing to the SLEEP register address or by
writing to the SLEEP_CFG register with SLP = 1. When
SHDN is asserted, the device is in sleep mode even if
the SLEEP or
SLEEP function on the UPIO is deassert-
ed. The SHDN bit is deasserted by writing to the
NORM_MD register or by other defined events. Events
that cause SHDN to be deasserted are a day alarm or
an edge on the UPIO wake-up pin causing wake-up to
be asserted. The power-on default is 0.
MSB
LSB
SLP (ADR0)
SOSCE
SCK32E
SPWME
SHDN
X
SLEEP_CFG Register (Power-On State: 1100 XXXX)
4Hz CLOCK
2-BIT COUNTER
X
WDE = 1
01
2
3
RESET
WATCHDOG
ADDRESS
01
2
WATCHDOG
ADDRESS
WATCHDOG
ADDRESS
01
0
1
2
0
750ms
250ms
SPI WRITES
D
Q
R
CK
DQ
Q
R
CK
DIVIDE-
BY-8192
32K
WDE
POR
WDW
WATCHDOG TIMER
4Hz
RESET
Figure 17. Watchdog Timer Architecture
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1359BETL+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換系統(tǒng) 16-Bit 2Ch .512ksps 3.6V Precision SoIC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MAX1359BETL+T | 功能描述:數(shù)據(jù)轉(zhuǎn)換系統(tǒng) 16-Bit 2Ch .512ksps 3.6V Precision SoIC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MAX1359BETL-T | 功能描述:數(shù)據(jù)轉(zhuǎn)換系統(tǒng) RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MAX135C/D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX135CP1 DC/94 | 制造商:INT 功能描述:135C |
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