參數(shù)資料
型號: MAX1441GUP/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 20/41頁
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準包裝: 2,500
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
27
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
SCT (01h, 01h)
Single Conversion Register (8-Bit Register)
Initialization
This register is cleared to 02h on all forms of reset.
Read/Write Access
Unrestricted read/write. See the following individual bit definitions for write restriction.
SCT.0–SCT
Single Conversion Trigger. Setting this bit to 1 initiates a conversion to an enabled channel (PDx = 0)
when the single conversion mode is enabled. Once set to 1, a write to this bit is ignored. This bit is
automatically cleared to 0 at the end of the conversion.
SCT.1–SCEN
Single Conversion Enable. Setting this bit to 1 enables the single conversion mode. Clearing this bit to
0 disables the single conversion mode.
SCT[7:2]
Reserved. Read returns 0.
CRNG (02h, 01h)
Input Range Register (8-Bit Register)
Initialization
This register is cleared to 22h on all forms of reset.
Read/Write Access
Unrestricted read/write.
CRNG[1:0]–
CRNG1[1:0]
CH1 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range.
CRNG1[1:0]
CAPACITANCE RANGE (pF)
00
5
01
10
20
11
20
CRNG[3:2]
Reserved. Read returns 0.
CRNG[5:4]–
CRNG2[1:0]
CH2 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range.
CRNG2[1:0]
CAPACITANCE RANGE (pF)
00
5
01
10
20
11
20
CRNG[7:6]
Reserved. Read returns 0.
PD (03h, 01h)
Power-Down Register (8-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read. Write to this register is unrestricted, unless otherwise stated in the following bit
definition.
PD.0–SB
Standby Enable. Setting this bit to 1 enables the standby mode for both channels. Clearing this bit to 0
disables the standby mode. When standby mode is enabled, the conversion occurs at a divided-down
rate as defined by DSB and SSB. Once set, this bit can be cleared by software. This bit is automatically
cleared to 0 if a wake-up event occurs.
PD.1–PD1
CH1 Power-Down. Setting this bit to 1 powers down CH1. Clearing this bit to 0 powers up CH1.
PD.2–PD2
CH2 Power-Down. Setting this bit to 1 powers down CH2. Clearing this bit to 0 powers up CH2.
PD[7:3]
Reserved. Read returns 0.
WU1 (04h, 01h)
CH1 Wake-Up Control Register (8-Bit Register)
Initialization
This register is cleared to 04h on all forms of reset.
Read/Write Access
Unrestricted read/write.
WU1.0–AE1
CH1 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up
threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection.
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