V
參數(shù)資料
型號: MAX1441GUP/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 38/41頁
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
6
Pin Configuration
Pin Description
20
19
18
17
16
15
14
1
2
3
4
5
6
7
VDD
DGND
OUT1
OUT2
P0.1/INT1/ TDO
P0.2/INT2/TDI
P0.3/TMS
P0.4
TOP VIEW
MAX1441
I.C.
AGUD2
AGUD1
RESET
13
8
SINPUT2
SINPUT1
12
9
AGND
VAA
11
10
N.C.
VBATT
P0.0/INT0/ TCK
TSSOP
PIN
NAME
FUNCTION
1
P0.4
CPU Port 0 Bit 4. Digital input/output.
2
P0.3/TMS
CPU Port 0 Bit 3/TMS. Digital input/output.
3
P0.2/INT2/TDI
CPU Port 0 Bit 2/TDI. Digital input/output with configurable edge-triggered interrupt.
4
P0.1/INT1/TDO
CPU Port 0 Bit 1/TDO. Digital input/output with configurable edge-triggered interrupt.
5
P0.0/INT0/TCK
CPU Port 0 Bit 0/TCK. Digital input/output with configurable edge-triggered interrupt.
6
RESET
Active-Low Reset Input. RESET requires an external pullup to VDD.
7
AGUD1
Active Guard 1. Driven guard (active shield) output for channel 1.
8
SINPUT1
Sensor Input 1. Capacitive sensor electrode input for channel 1.
9
VAA
Analog Power Supply. VAA is internally connected to the output of an on-chip 3.4V linear regulator.
Connect VAA to VDD. Bypass VAA with a 0.47FF capacitor to AGND as close to VAA as possible.
10
VBATT
Power-Supply Voltage. Input to the 3.4V on-chip linear regulator. Bypass VBATT to AGND with a
0.1FF capacitor as close to VBATT as possible.
11
N.C.
No Connection. Not internally connected. Leave N.C. unconnected.
12
AGND
Analog Ground. Connect AGND to DGND.
13
SINPUT2
Sensor Input 2. Capacitive sensor electrode input for channel 2.
14
AGUD2
Active Guard 2. Driven guard (active shield) output for channel 2.
15, 16
I.C.
Internally Connected. Leave unconnected.
17
OUT2
Open-Drain Output 2. CPU port 0 bit 6.
18
OUT1
Open-Drain Output 1. CPU port 0 bit 5.
19
DGND
Digital Ground. Connect DGND to AGND.
20
VDD
Digital Power Supply. Connect VDD to VAA. Bypass VDD with a 0.47FF capacitor to DGND as
close to VDD as possible.
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