參數(shù)資料
型號: MAX1441GUP/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/41頁
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關文件: Automotive Product Guide
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
17
Table 5. Special-Purpose Register Bit Description (continued)
REGISTER
DESCRIPTION
WDCN[5:4]–WD[1:0]
Watchdog Timer Mode Select Bits [1:0]. These bits are used to provide a user selection of watchdog
timer interrupt periods, which determine the watchdog timer interrupt timeout when the watchdog timer
is enabled. All watchdog timer reset timeouts follow the programmed interrupt timeouts by 512 times the
clock divide ratio oscillator cycles.
Mode select bit settings and the timeout values. Changing the WD1:0 bit settings resets the watchdog
timer unless the 512 clock reset counter has already started, in which case, changing the WD1:0 bits
does not affect the watchdog timer or reset counter.
These bits can only be written when simultaneously resetting the timer (RWT = 1). Otherwise, a
write to these control bits is ignored (i.e., user software sets the RWT bit and changes the WD
value in the same instruction).
WDCN.6–EWDI
Watchdog Interrupt Enable. Setting this bit to 1 enables interrupt requests generated by the watchdog
timer. Clearing this bit to 0 disables the interrupt requests. This bit is cleared following a power-on reset
and unaffected by all other resets.
WDCN.7–POR
Power-On Reset Flag. This bit indicates whether the last reset was a power-on reset. This bit is typically
interrogated following a reset. It must be cleared before the next reset of any kind for software to work
correctly. This bit is set following a power-on reset and unaffected by all other resets.
A0 (00h, 09h)
Accumulator 0 (16-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
A0[15:0]
Accumulator 0 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation
when activated by the accumulator pointer. Otherwise, it can be used as general-purpose working
register.
A1 (01h, 09h)
Accumulator 1 (16-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
A1[15:0]
Accumulator 1 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation
when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working
register.
A2 (02h, 09h)
Accumulator 2 (16-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
A2[15:0]
Accumulator 2 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation
when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working
register.
A3 (03h, 09h)
Accumulator 3 (16-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
A3[15:0]
Accumulator 3 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation
when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working
register.
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