參數(shù)資料
型號(hào): MAX19516ETM+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/35頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 2CH 100MSPS 48TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 100M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
______________________________________________________________________________________
15
Reference Input/Output (REFIO)
REFIO adjusts the reference potential, which, in turn,
adjusts the full-scale range of the ADC. Figure 4 shows
a simplified schematic of the reference system. An
internal bandgap voltage generator provides an internal
reference voltage. The bandgap potential is buffered
and applied to REFIO through a 10k
resistor. Bypass
REFIO with a 0.1F capacitor to GND. The bandgap
voltage is applied to a scaling and level-shift circuit,
which creates internal reference potentials that estab-
lish the full-scale range of the ADC. Apply an external
voltage on REFIO to trim the ADC full scale. The allow-
able adjustment range is +5/-15%. The REFIO-to-ADC
gain transfer function is:
VFS = 1.5 x [VREFIO/1.25] Volts
Programming and Interface
There are two ways to control the MAX19516 operating
modes. Full feature selection is available using the SPI
interface, while the parallel interface offers a limited set
of commonly used features. The programming mode is
selected using the SPEN input. Drive SPEN low for SPI
interface; drive SPEN high for parallel interface.
Parallel Interface
The parallel interface offers a pin-programmable inter-
face with a limited feature set. Connect SPEN to AVDD
to enable the parallel interface. See Table 1 for pin
functionality; see Figure 5 for a simplified parallel-inter-
face input schematic.
BANDGAP
REFERENCE
BUFFER
1.250V
REFIO
INTERNAL GAIN—BYPASS REFIO
EXTERNAL GAIN CONTROL—DRIVE REFIO
SCALE AND
LEVEL SHIFT
INTERNAL REFERENCE
(CONTROLS ADC GAIN)
10k
0.1
F
EXTERNAL BYPASS
Figure 4. Simplified Reference Schematic
36k
156k
CS
SCLK
SDIN
AVDD
29/32 AVDD
DECODER
TO
CONTROL
LOGIC
23/32 AVDD
3/32 AVDD
Figure 5. Simplified Parallel-Interface Input Schematic
SPEN
SDIN/FORMAT
SCLK/DIV
CS/OUTSEL
DESCRIPTION
0
SDIN
SCLK
CS
SPI interface active. Features are programmed through the
serial port (see the Serial Programming Interface section).
1
0
X
Two’s complement
1
AVDD
X
Offset binary
1
Unconnected
X
Gray code
1
X
0
X
Clock divide-by-1
1
X
AVDD
X
Clock divide-by-2
1
X
Unconnected
X
Clock divide-by-4
1
X
0
CMOS (dual bus)
1
X
AVDD
MUX CMOS (channel A data bus)
1
X
Unconnected
MUX CMOS (channel B data bus)
Table 1. Parallel-Interface Pin Functionality
X = Don’t care.
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