參數(shù)資料
型號(hào)： MAX19712ETN+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 34/36頁(yè)
文件大?。?/td> 0K
描述： IC ANLG FRNT END 56-TQFN
產(chǎn)品變化通告： Product Discontinuation 09/Jun/2011
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 2
功率（瓦特）： 50mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 56-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 56-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX19712
10-Bit, 22Msps, Full-Duplex
Analog Front-End
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 2)
Falling Edge of
CS/WAKE to Rising
Edge of First SCLK Time
tCSS
10
ns
DIN to SCLK Setup Time
tDS
10
ns
DIN to SCLK Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
25
ns
SCLK Pulse-Width Low
tCL
25
ns
SCLK Period
tCP
50
ns
SCLK to
CS/WAKE Setup Time
tCS
10
ns
CS/WAKE High Pulse Width
tCSW
80
ns
CS/WAKE High to DOUT
Active High
tCSD
Bit AD0 set
200
ns
CS/WAKE High to DOUT Low
(Aux-ADC Conversion Time)
tCONV
Bit AD0 set, no averaging, fCLK = 22MHz,
CLK divider = 8
4.3
s
DOUT Low to
CS/WAKE Setup
Time
tDCS
Bit AD0, AD10 set
200
ns
SCLK Low to DOUT Data Out
tCD
Bit AD0, AD10 set
14.5
ns
CS/WAKE High to DOUT High
Impedance
tCHZ
Bit AD0, AD10 set
200
ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
500
From shutdown to Tx mode, DAC settles to
within 10 LSB error
26.2
From aux-ADC enable to aux-ADC start
conversion
10
From shutdown to aux-DAC output valid
28
Shutdown Wake-Up Time
(With CLK)
tWAKE,SD
From shutdown to FD mode, ADC settles
to within 1dB SINAD, DAC settles to within
10 LSB error
500
s
From idle to Rx mode, ADC settles to within
1dB SINAD
7.2
From idle to Tx mode, DAC settles to 10
LSB error
5.1
Idle Wake-Up Time
(With CLK)
tWAKE,ST0
From idle to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
7.2
s
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參數(shù)描述
MAX19712EVCMODU+ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19712EVKIT 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 10-Bit 22Msps Full-Duplex Analog Front-End RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19712EVKIT+ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19713C/D+GG3 功能描述:ADC / DAC多通道 Ultra-Low Power AFE with Integrated Tx DACs Rx ADCs and Auxiliary Control Data Converters RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19713C/D-GG3 功能描述:ADC / DAC多通道 10-Bit 45Msps Full-Duplex Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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