![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/MAX3420EECJ-T_datasheet_98262/MAX3420EECJ-T_11.png)
USB Peripheral Controller
with SPI Interface
Test Circuits and Timing Diagrams
Figure 6. Rise and Fall Times
VOL
VOH
tRISE
tFALL
90%
10%
Figure 7. Load for D+/D- AC Measurements
MAX3420E
D+ OR D-
TEST
POINT
33
Ω
15k
Ω
CL
SCLK
SS
MOSI
MISO
tDS
tDH
tCL
tDO
tCH
tT
HIGH
IMPEDANCE
8
1
2
9
10
16
tL
tCSS
tCSW
tCP
HIGH
IMPEDANCE
Figure 9. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))
SCLK
MOSI
MISO
NOTES:
1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS
FOR FULL-DUPLEX MODE.
2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.
3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-RISING EDGE, THE MAX3420E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN
OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.
tDS
tDH
tCL
tCH
tDI
tOFF
tT
SS
HI-Z
8
1
2
9
10
16
tL
tCSW
tON
tCP
HIGH IMPEDANCE
Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))
MAX3420E
11
Maxim Integrated