參數(shù)資料
型號(hào): MAX3421EEHJ+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 12/28頁(yè)
文件大?。?/td> 0K
描述: IC USB PERIPH/HOST CNTRL 32TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
控制器類型: USB 外設(shè)控制器
接口: USB/串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 15mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
配用: MAX3421EVKIT-1+-ND - EVAL KIT FOR MAX3421E
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
2
Maxim Integrated
Features in Host Operation
o Eleven Registers (R21–R31) are Added to the
MAX3420E Register Set to Control Host Operation
o Host Controller Operates at Full Speed or Low
Speed
o FIFOS
SNDFIFO: Send FIFO, Double-Buffered 64-Byte
RCVFIFO: Receive FIFO, Double-Buffered 64-Byte
o Handles DATA0/DATA1 Toggle Generation and
Checking
o Performs Error Checking for All Transfers
o Automatically Generates SOF (Full-Speed)/EOP
(Low-Speed) at 1ms Intervals
o Automatically Synchronizes Host Transfers with
Beginning of Frame (SOF/EOP)
o Reports Results of Host Requests
o Supports USB Hubs
o Supports ISOCHRONOUS Transfers
o Simple Programming
SIE Automatically Generates Periodic SOF
(Full-Speed) or EOP (Low-Speed) Frame
Markers
SPI Master Loads Data, Sets Function Address,
Endpoint, and Transfer Type, and Initiates the
Transfer
MAX3421E Responds with an Interrupt and
Result Code Indicating Peripheral Response
Transfer Request Can be Loaded Any Time
SIE Synchronizes with Frame Markers
For Multipacket Transfers, the SIE
Automatically Maintains and Checks the
Data Toggles
Features in Peripheral Operation
o Built-In Endpoint FIFOS
EP0: CONTROL (64 bytes)
EP1: OUT, BULK or INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, BULK or INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, BULK or INTERRUPT (64 Bytes)
o Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrent with USB Transfers
o SETUP Data Has its Own 8-Byte FIFO, Simplifying
Firmware
The MAX3421E connects to any microprocessor (P)
using 3 or 4 interface pins (Figure 1). On a simple
microprocessor without SPI hardware, these can be
bit-banged general-purpose I/O pins. Eight GPIN and
eight GPOUT pins on the MAX3421E more than
replace the P pins necessary to implement the inter-
face. Although the MAX3421E SPI hardware includes
separate data-in (MOSI, master-out, slave-in) and data-
out (MISO, master-in, slave-out) pins, the SPI interface
can also be configured for the MOSI pin to carry bidi-
rectional data, saving an interface pin. This is referred
to as half-duplex mode.
Typical Application Circuits
3.3V
REGULATOR
SPI
3, 4
INT
USB
μP
MAX3421E
Figure 1. The MAX3421E Connects to Any Microprocessor
Using 3 or 4 Interface Pins
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