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參數(shù)資料
| 型號： | MAX3676EHJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK RECOVERY 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 托盤 |
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
_______________________________________________________________________________________
7
_______________Detailed Description
The block diagram in Figure 1 shows the MAX3676’s
architecture. It consists of a limiting-amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a PLL. The input stage
is selectable between a limiting amplifier or a simple
PECL input buffer. The limiting amplifier provides an
LOP monitor and an RSSI output. The PLL consists of a
phase/frequency detector (PFD), a loop filter amplifier,
and a voltage-controlled oscillator (VCO).
Limiting Amplifier
The MAX3676’s on-chip limiting amplifier accepts an
input signal level from 3.0mVP-P to 1.2VP-P. The amplifi-
er consists of a cascade of gain stages that include full-
wave logarithmic detectors. The combined small-signal
gain is approximately 42dB, and the -3dB bandwidth is
650MHz. Input-referred noise is typically 80μVRMS, pro-
viding excellent sensitivity for small-amplitude data
streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVP-P
(see the
Typical Operating Characteristics).
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC-coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the postamplifier block.
MAX3676
LOL
PHASE/FREQ
DETECTOR
POWER
DETECT
OFFSET
CORRECTION
FILTER
622.08MHz
LIMITER
42dB
BIAS
VCO
Σ
DQ
Q
I
CFILT
RSSI
INV
VTH
LOP
FIL+ FIL-
PHADJ+
DDI+
DDI-
INSEL
ADI-
ADI+
PHADJ-
1.23V
SDO+
SDO-
PECL
VCC
6k
Ω
6k
Ω
PECL
SCLKO+
SCLKO-
OLC+
OLC-
Figure 1. Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3676EHJ+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3676EHJ+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3676EHJ-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3677CTJ+ | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN |
| MAX3677CTJ+T | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel |
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