參數(shù)資料
型號: MAX3798ETJ+
廠商: Maxim Integrated Products
文件頁數(shù): 33/35頁
文件大?。?/td> 0K
描述: IC LIMITING AMP/VCSEL DVR 32TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
放大器類型: 限制
電路數(shù): 1
輸出類型: 差分
電流 - 電源: 97mA
電壓 - 電源,單路/雙路(±): 2.85 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 1387 (CN2011-ZH PDF)
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100
Ω, CAZ = 1nF, transmitter out-
put load is AC-coupled to differential 100
Ω (see Figure 1), typical values are at +25°C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DISABLE Input Low Voltage
VIL
0
0.8
V
DISABLE Input Impedance
RPULL
Internal pullup resistor
5.5
8
10.5
k
LOS, FAULT Output High Voltage
VOH
RLOS = 4.7k
- 10k
to VCC,
RFAULT = 4.7k
- 10k
to VCC
VCC -
0.5
VCC
V
LOS, FAULT Output Low Voltage
VOL
RLOS = 4.7k
- 10k
to VCC,
RFAULT = 4.7k
- 10k
to VCC
0
0.4
V
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
0.8
V
Input Hysteresis
VHYST
0.082
V
Input Leakage Current
IIL, IIH
VIN = 0V or VCC; internal pullup or pulldown
(75k
typical)
150
μA
Output High Voltage
VOH
External pullup of 4.7k
to VCC
VCC -
0.5
V
Output Low Voltage
VOL
External pullup of 4.7k
to VCC
0.4
V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 4)
SCL Clock Frequency
fSCL
400
1000
kHz
SCL Pulse-Width High
tCH
0.5
μs
SCL Pulse-Width Low
tCL
0.5
μs
SDA Setup Time
tDS
100
ns
SDA Hold Time
tDH
100
ns
SCL Rise to SDA Propagation
Time
tD
5ns
CSEL Pulse-Width Low
tCSW
500
ns
CSEL Leading Time Before the
First SCL Edge
tL
500
ns
CSEL Trailing Time After the
Last SCL Edge
tT
500
ns
SDA, SCL External Load
CB
Total bus capacitance on one line with
4.7k
pullup to VCC
20
pF
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
put and the bias current output must be connected to a separate supply in order to remove the modulation/bias current
portion from the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50
Ω load resistors
to a separate supply voltage.
Note 2: Guaranteed by design and characterization, TA = -40°C to +95°C.
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4: Test pattern is 00001111 at 4.25Gbps for MODE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for MODE_SEL = 1.
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