參數(shù)資料
型號(hào): MAX3815ACCM+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/11頁(yè)
文件大小: 0K
描述: IC DGTL VIDEO EQUALIZER 48TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
類型: 視頻均衡器
應(yīng)用: HDMI,DVI,接收器
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
8 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Applications Information
Typical shielded twisted pair (STP), unshielded twisted
pair (UTP), and twin-ax cables exhibit skin-effect losses,
which attenuate the high-frequency spectrum of a TMDS
signal, eventually causing data errors or even closing
the signal eye altogether given a long enough cable. The
MAX3815A recovers the data and opens the signal eye
through compensating equalization.
The basic TMDS interface is composed of four differential
serial links: three links carry serial data up to 2.25Gbps
each, and the fourth is a one-tenth-rate (0.1x) clock that
operates up to 225MHz. TMDS, as with analog nVGA
links, must handle a variety of resolutions and screen
update rates. The actual range of digital serial rates is
roughly 250Mbps to 2.25Gbps. For applications requir-
ing ultra-high resolutions (e.g., QXGA), a “dual-link” DVI
interface is used and is composed of six data links plus
the clock, requiring two MAX3815A ICs with the clock
going to both ICs. See Figure 2.
The MAX3815A can be used to extend any TMDS inter-
face as used under the following trademarked names:
DVI (digital visual interface), DFP (digital flat-panel),
PanelLink, ADC (Apple display connector), and HDMI
(high-definition multimedia interface).
Loss-of-Clock Signal (CLKLOS) Output
A loss-of-clock signal is indicated by the CLKLOS out-
put. A low level on CLKLOS indicates that the signal
power on the RXC_IN pins has dropped below a thresh-
old. When there is sufficient input voltage to the channel
(typically greater than 100mVP-P differential), CLKLOS is
high. The CLKLOS output is suitable for indicating prob-
lems with the transmission link caused by, for example,
a broken cable, a defective driver, or a lost connection
to the equalizer. Note that the loss-of-clock circuitry is
sensitive to a DC or AC voltage between the RXC_IN
pins. A DC or AC voltage greater than Q30mV (typical) is
sensed as an active clock signal.
Figure 2. Connection Scheme for MAX3815A in Dual Link
Application
DFP is a trademark of Video Electronics Standards Association (VESA).
ADC is a trademark of Apple Computer, Inc.
Figure 4. Back Termination Circuit
Figure 3. Simplified CLKLOS Output Circuit Schematic
D0
D1
D2
D3
D4
D5
D0
D1
D2
D3
D4
D5
CLK
MAX3815A
RX_OUT-
267
50
+3.3V
50
RX_OUT+
12.5mA
HDM/DVI
RECEIVER
VCC
CLKLOS
TO CHIP POWER-
CONTROL CIRCUITRY
4.7k
MAX3815A
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MAX3815ACCM+T 功能描述:IC DGTL VIDEO EQUALIZER 48TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話,手機(jī),視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
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