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參數(shù)資料
| 型號(hào)： | MAX5550ETE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | Quadruple Low-Power Differential Line Receiver 16-CDIP -55 to 125 |
| 中文描述： | SERIAL INPUT LOADING, 30 us SETTLING TIME, 10-BIT DAC, QCC16 |
| 封裝： | 3 X 3 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-220WEED-2, QFN-16 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 397K |
| 代理商： | MAX5550ETE |
M
Early STOP Conditions
The MAX5550 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (
Figure 4).
This condition is not allowed in the I
2
C format.
Repeated START Conditions
A repeated START (S
r
) condition is used when the bus
master is writing to several I
2
C devices and does not
want to relinquish control of the bus. The MAX5550’s
serial interface supports continuous write operations
with an S
r
condition separating them.
Acknowledge Bit (ACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5550 (slave) generate acknowledge bits. To gen-
erate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
10
______________________________________________________________________________________
S
P
Sr
SCL
SDA
Figure 3. START and STOP Conditions
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 4. Early STOP Conditions
SCL
SDA
S
P
Sr
t
SU:DAT
t
HD:DAT
t
RDA
t
RCL
t
FCL
t
HIGH
t
LOW
t
HIGH
t
LOW
t
FCL
t
RCL
t
SU:STO
t
HD:STA
t
FDA
t
SU:STA
Figure 2. I
2
C Serial-Interface Timing Diagram
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