參數(shù)資料
型號: MAX5550ETE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Quadruple Low-Power Differential Line Receiver 16-CDIP -55 to 125
中文描述: SERIAL INPUT LOADING, 30 us SETTLING TIME, 10-BIT DAC, QCC16
封裝: 3 X 3 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-220WEED-2, QFN-16
文件頁數(shù): 14/15頁
文件大?。?/td> 397K
代理商: MAX5550ETE
M
Power Sequencing
Ensure that the voltage applied to REFIN does not
exceed V
DD
at any time. If proper power sequencing is
not possible, connect an external Schottky diode
between REFIN and V
DD
to ensure compliance with the
absolute maximum ratings.
Power-Supply Bypassing and Ground
Management
Digital or AC transient signals on GND create noise at
the analog output. Return GND to the highest quality
ground plane available. For extremely noisy environ-
ments, bypass REFIN and V
DD
to GND with 1μF and
0.1μF capacitors with the 0.1μF capacitor as close to
the device as possible. Careful PC board ground layout
minimizes crosstalk between the DAC outputs and
digital inputs.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
14
______________________________________________________________________________________
CONTROLLER
DEVICE
DIN(0)
SCLK
CS
DOUT(0)
MAX5550
DIN(1)
SCLK
CS
DOUT(1)
MAX5550
DIN(2)
SCLK
CS
DOUT(2)
MAX5550
Figure 8. Daisy-Chain Configuration
15
16
14
13
5
6
7
C
S
8
S
F
O
O
1
3
V
DD
4
12
10
9
N.C.
GND
GND
REFIN
N.C.
DOUT/A1
MAX5550
D
F
2
11
N.C.
THIN QFN (3mm x 3mm)
TOP VIEW
Pin Configuration
Chip Information
PROCESS: BiCMOS
相關PDF資料
PDF描述
MAX5580-MAX5585 Quadruple Low-Power Differential Line Receiver 20-LCCC -55 to 125
MAX5580AETP Quadruple Low-Power Differential Line Receiver 16-CDIP -55 to 125
MAX5580AEUP Quadruple Low-Power Differential Line Receiver 16-CFP -55 to 125
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