參數(shù)資料
型號： MAX5550ETE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Quadruple Low-Power Differential Line Receiver 16-CDIP -55 to 125
中文描述： SERIAL INPUT LOADING, 30 us SETTLING TIME, 10-BIT DAC, QCC16
封裝： 3 X 3 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-220WEED-2, QFN-16
文件頁數(shù)： 9/15頁
文件大?。?/td> 397K
代理商： MAX5550ETE
I
2
C Compatibility (SPI/
I2C
= GND)
The MAX5550 is compatible with existing I
2
C systems
(
Figure 2). SCL and SDA are high-impedance inputs;
SDA has an open-drain output that pulls the data line
low during the ninth clock pulse. SDA and SCL require
pullup resistors (2.4k
or greater) to V
DD
. Optional
resistors (24
) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals. The communication protocol sup-
ports standard I
2
C 8-bit communications. The device’s
address is compatible with 7-bit I
2
C addressing proto-
col only. Ten-bit address formats are not supported.
Only write commands are accepted by the MAX5550.
Note:
I
2
C readback is not supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
The MAX5550 requires nine clock cycles to transfer
data into or out of the DAC register. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the
START and STOP
Conditions
section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), (a high-to-low transition on SDA with SCL high).
The master terminates a transmission with a STOP con-
dition (P), (a low-to-high transition on SDA while SCL is
high) (Figure 3). A START condition from the master
signals the beginning of a transmission to the
MAX5550. The master terminates transmission by issu-
ing a STOP condition. The STOP condition frees the
bus. If a repeated START condition (S
r
) is generated
instead of a STOP condition, the bus remains active.
M
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________
9
+1.25V
REFERENCE
I
FSADJ
R
FSADJ
FSADJ_
OUT_
V
DD
GND
CURRENT-SOURCE
ARRAY DAC
Figure 1. Reference Architecture and Output Current Adjustment
*
Negative output current values = 0
FULL-SCALE OUTPUT CURRENT (mA)*
1.5mA–3mA
2.5mA–5mA
1.500
2.500
1.875
3.125
2.250
3.750
2.625
4.375
3.000
5.000
*
See the command summary in Table 4.
R
FSADJ
(k
)
1mA–2mA
1.00
1.25
1.50
1.75
2.00
4.5mA–9mA
4.500
5.625
6.750
7.875
9.000
8mA–16mA
8.00
10.00
12.00
14.00
16.00
15mA–30mA
15.00
18.75
22.50
26.25
30.00
Calculated
40
35
30
25
20
1% EIA Std
40.2
34.8
30.1
24.9
20.0
Table 1. Full-Scale Output Current and R
FSADJ_
Selection Based on a +1.25V (typ)
Reference Voltage
DAC CODE
I
OUT
_
11 1111 1111
10 0000 0000
00 0000 0001*
00 0000 0000
0
Table 2. DAC Output Code Table
1023
1024
I
×
I
I
FS
OS
|
|
1023
1024
×
I
I
FS
OS
|
|
1023
1024
×
I
I
FS
OS
|
|
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