參數(shù)資料
型號(hào)： MAX5725AAUP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/35頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT SRL 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 4.5µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 1.08W
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電流，單極
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
20
Maxim Integrated
Table
2.
SPI
Commands
Summary
COMMAND
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DESCRIPTION
CONFIGURATION
AND
SOFTWARE
COMMANDS
WDOG
0
1
X
TIMEOUT
SELECTION[11:4]
TIMEOUT
SELECTION[3:0]
WD_MASK
Safety
Level
00:
Low
01:
Med
10:
High
11:
Max
X
Updates
watchdog
settings
and
safety
levels
REF
0
1
0
REF
Power
0=
DAC
1=
ON
REF
Mode
00
=
EXT
01
=
2.5V
10
=
2.0V
11
=
4.1V
X
Sets
the
reference
operating
mode.
REF
Power
(B18):
0=
Internal
reference
is
only
powered
if
at
least
one
DAC
is
powered
1=
Internal
reference
is
always
powered
SW_GATE_
CLR
0
1
0
1
0
1
0
1
0
1
0
Removes
any
existing
GATE
condition
SW_GATE_
SET
0
1
0
1
0
1
0
1
0
1
0
Initiates
a
GATE
condition
WD_REFRESH
0
1
0
1
0
1
0
1
0
1
0
1
0
Refreshes
the
watchdog
timer
WD_RESET
0
1
0
1
0
1
0
1
0
1
0
Reset
the
watchdog
time
out
alarm
status
and
refreshes
the
watchdog
timer
SW_CLEAR
0
1
0
1
0
1
0
1
0
1
0
1
0
Executes
a
software
clear
(all
CODE
and
DAC
registers
cleared
to
their
DEFAULT
values)
SW_RESET
0
1
0
1
0
1
0
1
0
1
0
1
0
Executes
a
software
reset
(all
CODE,
DAC,
and
control
registers
returned
to
their
power-on
reset
values)
CONFIG
0
1
0
1
0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
WDOG
Config.
00:
DIS
01:
GATE
10:
CLR
11:
HOLD
GATE_ENB
LDAC_ENB
CLEAR_ENB
X
Configures
selected
DAC
Watchdog,
GATE,
LOAD,
and
CLEAR
operations.
DACs
selected
with
a
1in
the
corresponding
DACn
bit
are
updated,
DACs
with
a
0
in
the
corresponding
DACn
bit
are
not
impacted)
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