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MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________
11
PIN
NAME
FUNCTION
1
RESET
Hardware Reset. Pull
RESET low for at least 300s to reset the device. All internal registers reset to
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of
RESET. Internally pulled up to VDD with 50k
resistor.
2
MIDSPAN
MIDSPAN Mode Input. An internal 50k
pulldown resistor to DGND sets the default mode to endpoint
PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
3
INT
Open-Drain Interrupt Output.
INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling
RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
4
SCL
Serial Interface Clock Line
5
SDAOUT
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical
Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I
2C-compatible system.
6
SDAIN
Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical
Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I
2C-compatible system.
7–10
A3, A2, A1, A0
Address Bits. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
high with an internal 50k
pullup resistor to VDD. The address values latch when VDD or VEE ramps
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
11–14
DET1, DET2,
DET3, DET4
Detection and Classification Voltage Outputs. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
15
DGND
Connect to Digital Ground
16
VDD
Positive Digital Supply. Connect to digital supply (referenced to DGND).
17–20
SHD1, SHD2,
SHD3, SHD4
Port Shutdown Inputs. Pull
SHD_ low to turn off the external FET on port_. Internally pulled up to VDD
with a 50k
resistor.
21
AGND
Analog Ground. Connect to the high-side analog supply.
22, 25,
29, 32
SENSE4, SENSE3,
SENSE2, SENSE1
MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and VEE (see the Typical Application Circuit).
23, 26,
30, 33
GATE4, GATE3,
GATE2, GATE1
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external FET (see the Typical
Application Circuit).
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100
to 100k). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
28
VEE
Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1F
capacitor between AGND and VEE.
35
AUTO
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5945 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
operational modes of the MAX5945. A 50k
internal pulldown resistor defaults AUTO low. AUTO
latches when VDD or Vramps up and exceeds its UVLO threshold or when the device resets.
Software commands can take the MAX5945 out of AUTO while AUTO is high.
36
OSC_IN
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz ±10%, 2VP-P
±5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below the OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
Pin Description