參數(shù)資料
型號(hào)： MAX7000S
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 14/62頁(yè)
文件大?。?/td> 1173K
代理商： MAX7000S
14
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs via the programmable interconnect array
(PIA). This global bus is a programmable path that connects any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
I/ O pins, and macrocell outputs feed the PIA, which makes the signals
available throughout the entire device. Only the signals required by each
LAB are actually routed from the PIA into the LAB.
Figure7
shows how
the PIA signals are routed into the LAB. An EEPROM cell controls one
input to a 2-input
AND
gate, which selects a PIA signal to drive into the
LAB.
Figure 7. PIA Routing
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA
has a fixed delay. The PIA thus eliminates skew between signals and
makes timing performance easy to predict.
I/O Control Blocks
The I/ O control block allows each I/ O pin to be individually configured
for input, output, or bidirectional operation. All I/ O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
CC
.
Figure 8
shows the I/ O
control block for the MAX 7000 family. The I/ O control block of EPM7032,
EPM7064, and EPM7096 devices has two global output enable signals that
are driven by two dedicated active-low output enable pins (
OE1
and
OE2
).
The I/ O control block of MAX 7000E and MAX 7000S devices has six
global output enable signals that are driven by the true or complement of
two output enable signals, a subset of the I/ O pins, or a subset of the I/ O
macrocells.
To LAB
PIA Signals
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