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| 型號： | MAX7000S |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數(shù)： | 45/62頁 |
| 文件大小： | 1173K |
| 代理商： | MAX7000S |
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Altera Corporation
45
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
Table 11
. See
Figure 13
for more
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The
t
LPA
parameter
must be added to this minimum width if the clear or reset signal incorporates the
t
LAD
parameter into the signal
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.
(5)
The
f
MAX
values represent the highest frequency for pipelined data.
(6)
Operating conditions: V
CCIO
= 3.3 V
±
10
%
for commercial and industrial use.
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The
t
LPA
parameter must be added to the
t
LAD
, t
LAC
, t
IC
, t
EN
,
t
SEXP
,
t
ACL
, and
t
CPPW
parameters for macrocells
running in the low-power mode.
Tables 32
and
33
show the EPM7192S AC operating conditions.
t
PRE
t
CLR
t
PIA
t
LPA
Register preset time
2.4
3.0
3.0
4.0
ns
Register clear time
2.4
3.0
3.0
4.0
ns
PIA delay
(7)
1.6
2.0
1.0
2.0
ns
Low-power adder
(8)
11.0
10.0
11.0
13.0
ns
Table 31. EPM7160S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min
Max
Min
Max
Min
Max
Min
Max
Table 32. EPM7192S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
t
PD1
t
PD2
Input to non-registered output
C1 = 35 pF
7.5
10.0
15.0
ns
I/O input to non-registered
output
C1 = 35 pF
7.5
10.0
15.0
ns
t
SU
t
H
t
FSU
Global clock setup time
4.1
7.0
11.0
ns
Global clock hold time
0.0
0.0
0.0
ns
Global clock setup time of fast
input
3.0
3.0
3.0
ns
t
FH
Global clock hold time of fast
input
0.0
0.5
0.0
ns
t
CO1
t
CH
Global clock to output delay
C1 = 35 pF
4.7
5.0
8.0
ns
Global clock high time
3.0
4.0
5.0
ns
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