(VAVDD
參數(shù)資料
型號: MAX7456EVKIT+
廠商: Maxim Integrated Products
文件頁數(shù): 34/44頁
文件大?。?/td> 0K
描述: KIT EVAL FOR MAX7456
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,屏幕顯示器(OSD)
嵌入式: 是,MCU,16 位
已用 IC / 零件: MAX7456
主要屬性: NTSC/PAL 單通道單色屏幕顯示器(OSD),帶集成視頻驅(qū)動(dòng)器
次要屬性: GUI,SPI 接口
已供物品:
產(chǎn)品目錄頁面: 1424 (CN2011-ZH PDF)
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
TIMING CHARACTERISTICS
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
SCLK Period
tCP
100
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup
tCSS0
30
ns
CS Fall After SCLK Rise Hold
tCSH0
0ns
CS Rise to SCLK Setup
tCSS1
30
ns
CS Rise After SCLK Hold
tCSH1
0ns
CS Pulse-Width High
tCSW
100
ns
SDIN to SCLK Setup
tDS
30
ns
SDIN to SCLK Hold
tDH
0ns
SDOUT Valid Before SCLK
tDO1
20pF to ground
25
ns
SDOUT Valid After SCLK
tDO2
20pF to ground
0
ns
CS High to SDOUT High
Impedance
tDO3
20pF to ground
300
ns
CS Low to SDOUT Logic Level
tDO4
20pF to ground
20
ns
HSYNC, VSYNC, AND LOS TIMING
LOS, VSYNC, and HSYNC Valid
before CLKOUT Rising Edge
tDOV
20pF to ground
30
ns
NTSC external sync mode, Figure 4
375
VOUT Sync to VSYNC Falling
Edge Delay
tVOUT-VSF
PAL external sync mode, Figure 6
400
ns
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OSD CHARACTERISTICS
OSD Rise Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60
ns
OSD Fall Time
OSD insertion mux register
OSDM[5,4,3] = 011b
60
ns
OSD Insertion Mux Switch Time
OSD insertion mux register
OSDM[2,1,0] = 011b
75
ns
MAX7456
4
Maxim Integrated
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