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參數(shù)資料
| 型號(hào)： | MAX9222ETM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable DC-Balance 21-Bit Deserializers |
| 中文描述： | QUAD LINE RECEIVER, PQCC48 |
| 封裝： | 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-48 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 904K |
| 代理商： | MAX9222ETM |
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M
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________
9
channel is five. Limiting the DSV and choosing the cor-
rect coupling capacitors maintains differential signal
amplitude and reduces jitter due to droop on AC-cou-
pled links.
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9210/
MAX9212/MAX9214/MAX9216/MAX9220/MAX9222
deserializers whether the data bits are inverted (see
Figures 9 and 10). The deserializer restores the original
state of the parallel data. The LVDS clock signal alter-
nates duty cycles of 4/9 and 5/9, which maintain DC
balance.
TxIN_ IS DATA FROM THE SERIALIZER.
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
+
-
RxCLK IN
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN0
TxIN1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN7
TxIN8
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxIN0
RxIN1
RxIN0
RxIN2
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
DCA0
DCB1
DCA1
DCB2
DCA2
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN2
TxIN3
TxIN4
DCA0
TxIN5
TxIN6
DCB0
TxIN9
TxIN10
TxIN11
DCA1
TxIN12
TxIN13
DCB1
TxIN16
TxIN17
TxIN18
DCA2
TxIN19
TxIN20
DCB2
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
DCB0
RxCLK IN
RxIN1
RxIN0
RxIN2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
+
-
Figure 10. Deserializer Serial Input in DC-Balanced Mode
0.8V
PWRDWN
RxCLK IN
RxOUT_
RxCLK OUT
RPDD
HIGH-Z
Figure 8. Power-Down Delay
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9216ETM | Programmable DC-Balance 21-Bit Deserializers |
| MAX922CUA | Ultra Low-Power, Single/Dual-Supply Comparators |
| MAX921-MAX924 | Ultra Low-Power, Single/Dual-Supply Comparators |
| MAX922 | Ultra Low-Power, Single/Dual-Supply Comparators |
| MAX923 | Ultra Low-Power, Single/Dual-Supply Comparators |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9222EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9222EUM+ | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+D | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Rail/Tube |
| MAX9222EUM+T | 制造商:Maxim Integrated Products 功能描述:LVDS DESERLIZER 48TSSOP - Tape and Reel |
| MAX9222EUM+TD | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
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