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參數(shù)資料
型號(hào): MAX9257AGTL/V+
廠商: Maxim Integrated Products
文件頁數(shù): 19/53頁
文件大小: 0K
描述: IC SERDE PROG UART/I2C 40TQFN
標(biāo)準(zhǔn)包裝: 60
系列: *
Maxim Integrated Products 26
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
LVDS Serial Data
Serial LVDS data is transmitted least significant bit (LSB)
to most significant bit (MSB) as shown in Tables 5 through
13. The ECU at startup can program the parallel word
width, serial frequency range, parity, spread-spectrum,
and pixel clock frequency range (see the MAX9257A
Pixel Clock Frequency Range
The devices each have registers that can be configured
at startup. Depending on the word length, the MAX9257A
multiplies PCLK_IN (pixel clock) by 12, 14, 16, 18, or
20 using an internal PLL to generate the serial clock.
Use Table 20 for proper selection of available PCLK fre-
quency and serial-data ranges. Parallel data is serialized
using the serial-clock and serialized bits are transmitted
at the MAX9257A LVDS outputs. The devices support
a wide range for PCLK_IN (Table 14). If the pixel clock
frequency needs to change to a frequency outside the
programmed range, the ECU must program both the
MAX9257A and the MAX9258A in the same control chan-
nel session.
Serial-Data Rate Range
The word length and pixel clock is limited by the maxi-
mum serial-data rate of 840Mbps. The following formula
shows the relation between word length, pixel clock, and
serial clock:
Serial-word length x pixel clock = serial-data rate =
840Mbps
For example, if PCLK_IN is 70MHz, the serial-word length
has to be 12 bits including DC balance bits if parity is not
enabled to keep the serial-data rate under 840Mbps. If
the serial-word length is 20 bits, the maximum PCLK_IN
frequency is 42MHz. The serial-data rate can vary from
60Mbps to 840Mbps and can be programmed at power-
up (Table 15). Use Table 20 for proper selection of avail-
able PCLK frequency and serial data ranges. Operating
in the incorrect range for either the serial-data rate or
PCLK_IN can result in excessive current dissipation and
failure of the MAX9258A to lock to the MAX9257A.
LVDS Common-Mode Bias
The output common-mode bias is 1.2V at the LVDS
inputs on the MAX9258A and LVDS outputs on the
MAX9257A. No external resistors are required to provide
bias for AC-coupling the LVDS inputs and outputs.
Table 11. Format for 18-Bit Serial-Word Length with Parity (Parallel-Word Width = 14)
Table 12. Format for 16-Bit Serial-Word Length with Parity (Parallel-Word Width = 12)
Table 13. Format for 14-Bit Serial-Word Length with Parity (Parallel-Word Width = 10)
Table 14. MAX9257A Pixel Clock Range
(PCLKIN)
Table 15. Serial-Data Rate Range
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NAME
PR
PRB
EN0
EN1 HSYNC
VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
PR
PRB
EN0
EN1 HSYNC
VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME
PR
PRB
EN0
EN1 HSYNC
VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
FREQUENCY (MHz)
PRATE (REG0[7:6])
5–10
00
10–20
01
20–40
10
40–70
11
SERIAL-DATA RATE (Mbps)
SRATE (REG0[5:4])
60–100
00
100–200
01
200–400
10
400–840
11
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MAX9257GCM/V+T 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
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