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參數(shù)資料
型號(hào): MAX9257AGTL/V+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 36/53頁(yè)
文件大小: 0K
描述: IC SERDE PROG UART/I2C 40TQFN
標(biāo)準(zhǔn)包裝: 60
系列: *
Maxim Integrated Products 41
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
Applications Information
PRBS Test
The devices have built-in circuits for testing bit errors
on the serial link. The MAX9257A has a PRBS generator
and the MAX9258A has a PRBS checker. The length of
the PRBS pattern is programmable from 221 to 235 word
length or continuous by programming REG9[7:4] in the
MAX9257A. In case of errors, errors are counted in the
MAX9258A PRBSERR register (REG12), and the ERROR
output on the MAX9258A goes low. To start the test, the
ECU writes a 1 to PRBSEN bit of both the MAX9257A
and the MAX9258A. The PRBS test can be performed
with or without spread spectrum. If the PRBS test is
programmed to run continuously, the MAX9257A must
be powered down to stop the test. When programmed
for a finite number of repetitions, the control channel is
enabled after the PRBS test finishes and serialization
enable (SEREN) is reset to 0. To start normal operation,
the ECU must disable PRBSEN and enable SEREN.
Video Data Parity
Parity protection of video data is programmable for par-
allel-word widths of 16 bits or less. When programmed,
two parity bits are appended to each parallel word
latched into the MAX9257A. In the MAX9258A, a 16-bit
parity error counter logs parity errors. The ERROR out-
put on the MAX9258A goes low if parity errors exceed a
programmable threshold.
Activity Detector
Most applications use the default activity-detector set-
tings. If there is excessive noise on the link when the link
is not driven (during control channel mode), increase
the activity-detector offset to filter out noise amplitudes.
Using a larger offset threshold affects the maximum data
rate available. Table 32 lists the maximum recommended
data rate at different input offset settings for a 150mV
peak input signal.
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two from
18MHz to 42MHz capacitors are sufficient for isolation,
but four capacitors—two at the serializer output and two at
the deserializer input—provide protection if either end of
the cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
Selection of AC-Coupling Capacitors
See Figure 31 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequency.
The plot shows minimum capacitor values for two- and
four-capacitor-per-link systems. To block the highest
common-mode frequency shift, choose the minimum
capacitor value shown in Figure 31. In general, 0.1FF
capacitors are sufficient.
Table 32. Maximum Data Rate at Different
Input Offset Settings
Figure 31. AC-Coupling Capacitor Values vs. Clock Frequency
from 18MHz to 42MHz
OFFSET BITS
(REG1[4:3)
TYPICAL INPUT
OFFSET (mV)
MAXIMUM
FREQUENCY (Mbps)
00
23
780
01
11
940
10
59
520
11
75
400
AC-COUPLING CAPACITOR VALUE
vs. SERIAL-DATA RATE
SERIAL-DATA RATE (Mbps)
CAPACITOR
VALUE
(nF)
780
720
660
600
540
480
420
20
40
60
0
360
840
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
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