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參數(shù)資料
| 型號： | MAX9257AGTL/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERDE PROG UART/I2C 40TQFN |
| 標準包裝： | 60 |
| 系列： | * |
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Maxim Integrated Products 27
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
LVDS Termination
Terminate the LVDS link at both ends with the charac-
teristic impedance of the transmission line (typically
100O differential). The LVDS inputs and outputs are high
impedance to GND and differentially.
Spread-Spectrum Selection
The devices each have spread-spectrum options. Both
should not be turned on at the same time. When the
MAX9257A is programmed for spread spectrum, the
MAX9258A tracks and passes the spread to its clock and
data outputs. The MAX9257A/MAX9258A are both center
spread (Figure 21). The control channel does not use
spread spectrum, but has slower transition times.
MAX9258A Spread Spectrum
The MAX9258A features a programmable spread-spectrum
clock and data outputs for reduced EMI. The single-ended
data outputs are programmable for no spread, Q2%, or
Q
4% (see the Typical Operating Characteristics) around the
recovered pixel clock frequency. The output spread is pro-
grammed in register REG1[7:6]. Table 17 shows the spread
options, and Table 18 shows the various modulation rates.
MAX9257A Spread Spectrum
The MAX9257A features programmable spread spec-
trum for the LVDS outputs. Table 19 shows various
spread options, and Table 20 shows the various modu-
lation rates. Only one device (the MAX9257A or the
MAX9258A) should be programmed for spread spectrum
at a time. If the MAX9257A is programmed for spread,
the MAX9258A tracks and passes the spread to the data
and clock outputs. The PRATE range of 00 and 01 (5MHz
≤ PCLK ≤ 20MHz) supports all the spread options. The
PRATE range of 10 and 11 (20MHz ≤ PCLK ≤ 70MHz)
requires that the spread be 2% or less.
Pixel Clock Jitter Filter
The MAX9257A has a PLL to filter high-frequency pixel
clock jitter on PCLK_IN. The FPLL can be bypassed by
writing 1 to REG4[2]. The FPLL improves the MAX9258A’s
data recovery by filtering out the high-frequency compo-
nents from the pixel clock that the MAX9258A cannot
track. The 3dB bandwidth of the FPLL is 100kHz (typ).
Figure 21. Simplified Modulation Profile for the MAX9257A/
MAX9258A
Table 16. Parallel-Word Width
Table 17. MAX9258A Spread
Table 18. MAX9258A Modulation Rate
Table 19. MAX9257A LVDS Output Spread
PARALLEL-WORD WIDTH
PWIDTH (REG0[2:0])
10
000
12
001
14
010
16
011
18
1XX
PRATE (REG1[7:6])
SPREAD (%)
00
Off
01
Q
2
10
Off
11
Q
4
PRATE
(REG1[7:6])
MODULATION RATE
fSSM RANGE (kHz)
00
PCLK/312
16 to 32
01
PCLK/520
19.2 to 38.5
10
PCLK/1040
19.2 to 38.5
11
PCLK/1248
32 to 56
REG1[7:5]
SPREAD (%)
000
Off
001
Q
1.5
010
Q
1.75
011
Q
2
100
Off
101
Q
3
110
Q
3.5
111
Q
4
FREQUENCY
TIME
fSPREAD (MAX)
fPCLK_IN
fSPREAD (MIN)
1/fSSM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9257AGTV | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Fully Programmable Serializer/Deserializer with UART/I2C Control Channel |
| MAX9257EVKIT+ | 功能描述:界面開發(fā)工具 MAX9257 Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| MAX9257GCM/V+ | 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9257GCM/V+T | 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9257GCM+ | 功能描述:串行器/解串器 - Serdes Prog Serializer / Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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