參數(shù)資料
型號(hào)： MAX9258GCM/V+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 0K
描述： IC SER/DESER PROG 48-LQFP
其它有關(guān)文件： Automotive Product Guide
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 250
功能： 串行器/解串器
數(shù)據(jù)速率： 840Mbps
輸入類(lèi)型： 串行
輸出類(lèi)型： LVDS
輸入數(shù)： 1
輸出數(shù)： 16
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
MAX9257/MAX9258
case,
ERROR deasserts high after next video phase
starts if video parity errors were the only reason that
ERROR was asserted low. To report parity errors in
bypass mode, program autoerror reset (AER) to 1
(REG1[5] = 1).
Autoerror Reset
The default method to reset errors is to read the respec-
tive error registers in the MAX9258 (registers 10, 11, and
13). If errors were present before the next control chan-
nel, the error count gets incremented to the previous
number. By setting the autoerror reset (AER) bit to 1, the
error registers reset when the control channel ends.
Setting AER to 1 does not reset PRBS errors.
PRBS Errors
During the PRBS test, the MAX9258 checks received
PRBS data words by comparing them to internally gener-
ated PRBS data. Detected errors are counted in the PRBS
error register (REG12) in the MAX9258. Whenever the
number of detected PRBS errors is more than 0,
ERROR
asserts low. The PRBS error register is reset when ECU
writes a 0 to PRBSEN register (REG4[0]). In this case,
ERROR deasserts high immediately if PRBS errors were
the only reason that
ERROR was asserted low.
Short Synchronization Pattern
The short synchronization pattern is part of the handshak-
ing procedure between the MAX9257 and MAX9258 after
the control channel phase. It is used to resynchronize the
MAX9258’s clock and data recovery circuit to the
MAX9257 before the video phase begins. The MAX9257
transmits the short synchronization pattern when it
receives the lock frame from the MAX9258. The length of
short synchronization pattern is dependant on the PRATE
range. When PRATE is 00 or 01, the short synchroniza-
tion pattern consists of 546 words and when PRATE is 10
or 11, the short synchronization pattern consists of 1090
words. Every word is one pixel clock period.
Long Synchronization Pattern
At power-up or when the MAX9257 does not receive a
lock frame from the MAX9258, the MAX9257 transmits a
long synchronization pattern. The long synchronization
pattern consists of 17,410 words. Every word is one
pixel clock period. When REM is high, if synchroniza-
tion is not achieved after 62 attempts, the MAX9257
resets SEREN to 0 so that the control channel stays
open to allow troubleshooting. When REM is low, the
MAX9257/MAX9258 continuously tries to reestablish the
connection.
Lock Verification (Handshaking)
At the end of every vertical blanking time, the MAX9257
verifies that the MAX9258 did not lose lock. The
MAX9258 handshakes with the MAX9257 to indicate
lock status. The handshaking occurs after the channel
closes (Figures 22 and 23). If the number of decoding
errors in a time window did not exceed a certain thresh-
old during the last video phase, the MAX9258 sends
back the lock frame that indicates lock. If the MAX9257
receives the lock frame, the MAX9257 transmits a short
synchronization pattern. The MAX9258 features a pro-
prietary VCO mechanism that prevents frequency drift
while in the control channel. This allows for successful
resynchronization after extended use of control chan-
nel. If the number of decoding errors in a time window
exceeds a certain threshold, the MAX9258 loses lock,
LOCK goes low, and the lock frame is not sent. The
MAX9258 also loses lock if handshaking is not suc-
cessful. If the MAX9257 does not receive the lock
frame, it transmits a long synchronization pattern before
the start of next video phase. When REM = 1, if the lock
frame is not received by the MAX9257 after 62 consec-
utive attempts to synchronize, SEREN is disabled so
that the control channel opens permanently for trou-
bleshooting.
Link Status (LOCK and CCEN)
The LOCK output indicates whether the MAX9258 is
locked to the MAX9257. LOCK is an open-drain output
that needs to be pulled up to VCC. LOCK asserts low to
indicate that the MAX9258 is not locked to the
MAX9257 and high when it is. In the control channel
phase, LOCK stays high if LOCK is high in the video
phase. While in the control channel phase, the
MAX9258 PLL frequency is held constant, PCLK output
is active and data outputs are frozen at their last valid
value before entering the control channel. CCEN output
indicates whether the MAX9257/MAX9258 are in the
control channel phase or video phase. CCEN goes high
when the MAX9257/MAX9258 are in the control channel
phase (Table 27). Only at initial power-up, CCEN goes
high before communication in the control channel is
ready (see the
Link Power-Up section).
32
______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
LOCK
CCEN
INDICATION
1
0
LVDS channel active
1
Control channel active
0
X
PLL loss of lock
Table 27. Link Status
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