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參數(shù)資料
| 型號： | MAXQ7665BATM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/47頁 |
| 文件大小： | 0K |
| 描述： | IC MCU-BASED DAS 16BIT 48-TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MAXQ® |
| 核心處理器： | RISC |
| 芯體尺寸： | 16-位 |
| 速度： | 8MHz |
| 連通性： | CAN，LIN，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 8 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 256 x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
______________________________________________________________________________________
23
As DVDD continues to fall below the DVDD BOR thresh-
old set by the VDBR bits, the RESET pin is pulled low,
C and peripheral activity stops, and most, but not all
of the register bits are set to their default state. This
includes the VDBR bits, which retain their value if DVDD
falls below the BOR threshold, but not below the POR
threshold.
Once DVDD has entered BOR, there are a few possible
scenarios:
If DVDD remains below the BOR threshold, the
RESET pin remains low, and the C remains in the
reset state.
If DVDD stops falling before reaching the POR
threshold, then begins rising above the BOR thresh-
old, the RESET pin is released, and the C jumps to
the reset vector (8000h in the utility ROM). This is
similar to the DVDD power-up case described in the
previous scenario, except there is no power-up
counter delay and some of the register bits are set
to BOR values rather than POR values. See Tables 3
and 5 for the reset behavior of specific bits. In par-
ticular, the retained VDBR setting, if higher than the
default value of 00b, allows a potentially more robust
brownout recovery closer to or above the minimum
flash operating level of +3.0V.
If DVDD falls below the 1.2V POR threshold, all register
bits are reset, and any DVDD recovery from that point
is identical to the power-up case described above.
See Tables 3 and 5 for reset behavior of specific bits.
Refer to the
MAXQ7665/MAXQ7666 User’s Guide for
detailed programming information, and a more thor-
ough description of POR and brownout behavior.
Internal 3.3V Linear Regulator
The MAXQ7665A–MAXQ7665D core logic supply,
DVDD, can be supplied by a 3.3V external supply or the
on-chip 3.3V, 50mA linear regulator. To use the on-chip
linear regulator, ensure the DVDDIO supply can support
a load of approximately 50mA and connect digital input
REGEN to GNDIO. If using an external supply, connect
the regulated 3.3V supply to DVDD and connect digital
input REGEN to DVDDIO. If the linear regulator is not
used, bring up DVDDIO before DVDD.
System Clock Generator
The MAXQ7665A–MAXQ7665D oscillator module is the
master clock generator that supplies the system clock
for the C core and all of the peripheral modules. The
high-frequency (HF) oscillator is designed to operate
with an 8MHz crystal. Alternatively, the on-chip RC
oscillator can be used in applications that do not
require precise timing. Due to its RISC design, the
MAXQ7665A–MAXQ7665D execute most instructions in
a single SYSCLK period. The oscillator module contains
all of the primary clock-generation circuitry. Figure 6
shows a block diagram of the system clock module.
The MAXQ7665A–MAXQ7665D contain many features
for generating a master clock signal timing source:
Internal, fast-starting, 7.6MHz RC oscillator elimi-
nates external crystal
Internal high-frequency oscillator that can drive an
external 8MHz crystal
External high-frequency clock input (8MHz)
Selectable internal capacitors for HF crystal oscillator
Power-up timer
Power-saving management modes
Fail-safe modes
Watchdog Timer
The watchdog timer serves as a time-base generator,
an event timer, or a system supervisor. The primary
function of the watchdog timer is to supervise software
execution, watching for stalled or stuck software. The
watchdog timer performs a controlled system restart
when the P fails to write to the watchdog timer register
before a selectable timeout interval expires. In some
designs, the watchdog timer is also used to implement
a real-time operating system (RTOS) in the C. When
used to implement an RTOS, a watchdog timer typically
has four objectives:
1) To detect if a system is operating normally
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or
more tasks
4) To detect if some lower priority tasks are not getting
to run because of higher priority tasks
CD0
SYSCLK
MUX
HFRCCLK
CLOCK
DIVIDE
HF
XTAL
OSC
RC
OSC
XIN
XOUT
XT
EXTHF
RCE
HFE
Figure 6. High-Frequency and RC Oscillator Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAXQ7665C | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems |
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| MAXQ7665DATM+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems |
| MAXQ7665EVKIT# | 功能描述:開發(fā)板和工具包 - 其他處理器 Programmers, Development Systems RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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