參數(shù)資料
型號: MAXQ7665BATM+T
廠商: Maxim Integrated Products
文件頁數(shù): 22/47頁
文件大?。?/td> 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
標準包裝: 2,500
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 8MHz
連通性: CAN,LIN,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 256 x 16
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
______________________________________________________________________________________
29
TAP controller (see Figure 12). The shift registers serve
as transmit-and-receive data buffers for a debugger.
From a JTAG perspective, shift registers are user-
defined optional data registers. The bypass register
and the instruction register, for example, are realized
as a set of shift-register-based elements connected in
parallel between a common serial input (TDI) and a
common serial output (TDO). The instruction register,
through the TAP controller, selects one of the registers
to form an active serial path.
The maximum TCK clock frequency must be below
1/8 of the system clock frequency to work properly.
The TAP operates asynchronously with on-chip sys-
tem logic and may be affected by the timing relation-
ship between the on-chip state machines and the
TAP. The on-chip state machines are clocked by the
system clock.
The four digital I/Os that form the TAP module are
described as follows:
TDO—Serial output signal for test instruction and
data. Data is driven out only on the falling edge of
TCK and is forced in an inactive state when it is idle.
This signal is used to serially transfer internal data to
the host. Data is transferred LSB first.
TDI—Serial input signal for test instruction and data.
Data should be driven in only on the rising edge of
TCK. This signal is used to serially transfer data from
765
432
10 S1 S0
432
10
SYSTEM PROGRAMMING REGISTER
2
PO.0/TDO
10
PO.2/TDI
PO.1/TMS
PO.3/TCK
DVDDIO
INSTRUCTION REGISTER
POWER-ON
RESET
TAP
CONTROLLER
BYPASS
DEBUG REGISTER
SHADOW REGISTER
DVDDIO
READ
WRITE
DVDDIO
UPDATE-DR
MAXQ7665A–MAXQ7665D
MUX
DVDDIO
MUX
TO DEBUG
ENGINE
Figure 12. JTAG Interface Block Diagram
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參數(shù)描述
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