參數(shù)資料
型號: MAXQ7665BATM+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/47頁
文件大?。?/td> 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
標(biāo)準(zhǔn)包裝: 2,500
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 8MHz
連通性: CAN,LIN,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 256 x 16
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
As illustrated in Figure 7, the high-frequency internal
RC oscillator (HFRCCLK) drives the watchdog timer
through a series of dividers. The divider output is pro-
grammable and determines the timeout interval. When
enabled, the interrupt flag WDIF is set when a timeout
is reached. A system reset then occurs after a time
delay (based on the divider ratio).
The watchdog timer functions as the source of both the
watchdog interrupt and the watchdog reset. The inter-
rupt timeout has a default divide ratio of 212 of the HFR-
CCLK, with the watchdog reset set to timeout 29 clock
cycles later. With the nominal RC oscillator value of
7.6MHz, an interrupt timeout occurs every 539s, fol-
lowed by a watchdog reset 67.4s later. The watchdog
timer is reset to the default divide ratio following any
reset. Using the WD0 and WD1 bits in the WDCN regis-
ter, other divide ratios can be selected for longer
watchdog interrupt periods. If the WD[1:0] bits are
changed before the watchdog interrupt timeout occurs
(i.e. before the watchdog reset counter begins), the
watchdog timer count is reset. All watchdog timer reset
timeouts follow the programmed interrupt timeout 512
source clock cycles later. For more information on the
MAXQ7665A–MAXQ7665D watchdog timer, refer to the
MAXQ7665/MAXQ7666 User’s Guide.
Timer and PWM
The MAXQ7665A–MAXQ7665D include three 16-bit
timer channels. Each timer is a type 2 timer implement-
ed in the MAXQ family (see Figure 8). Two of the timers
are accessible through I/Os, and one is accessible only
through software. Type 2 timers are auto-reload 16-bit
timers/counters offering the following functions:
8-bit/16-bit timer/counter
Up/down auto-reload
Counter function of external pulse
Capture
Compare
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
24
_______________________________________________________________________________________
EDGE
DETECTION AND
GATING
TIMER EVENT
CCF[1:0]
G2EN
TR2
SS2
T2POL[0]
T2CL
T2MD
T2L COMPARE MATCH
T2H:T2L COMPARE MATCH OR
T2H COMPARE MATCH
T2L OVERFLOW
T2H:T2L OVERFLOW OR
T2H OVERFLOW
TR2L
T2CLK
T2L
T2RL
T2CH
T2H
T2RH
C/T2
Figure 8. Type 2 Timer Functional Diagram
EWDI
WD0
RWT
WD1
HFRCCLK
(7.6MHz)
INTERRUPT
WTRF
RESET
WDIF
TIMEOUT
TIME
212
DIV 212
DIV 23
215 218 221
EWT
RESET
Figure 7. Watchdog Functional Diagram
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