參數(shù)資料
型號: MB8116160A-60
廠商: Fujitsu Limited
英文描述: CMOS 1 M ×16 BIT Fast Page Mode DRAM(CMOS 1 M ×16 位快速頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 1米× 16位快速頁面模式的DRAM的CMOS(1米× 16位快速頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 19/25頁
文件大?。?/td> 330K
代理商: MB8116160A-60
19
MB8116160A-60/MB8116160A-70
A
0
to A
11
V
IH
V
IL
V
OH
V
OL
RAS
V
IH
V
IL
DQ
(Output)
Fig. 13 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
HIGH-Z
ROW ADDRESS
t
RC
t
RAS
t
RP
t
RPC
t
RAH
t
ASR
t
CRP
t
CRP
t
OFF
t
OH
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4096 row
addresses every 65.6-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be re-
freshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
V
OH
V
OL
RAS
V
IH
V
IL
DQ
(Output)
Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
“H” or “L”
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS
is held Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address
counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented
in preparation for the next CAS-before-RAS refresh operation.
HIGH-Z
t
RC
t
RAS
t
RP
t
RPC
t
CHR
t
CSR
t
CPN
t
OFF
t
OH
“H” or “L”
LCAS
or
UCAS
V
IH
V
IL
LCAS
or
UCAS
V
IH
V
IL
相關(guān)PDF資料
PDF描述
MB8116160A-70 CMOS 1 M ×16 BIT Fast Page Mode DRAM(CMOS 1 M ×16 位快速頁面存取模式動態(tài)RAM)
MB8116165A-60 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM)
MB8116165A-70 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM)
MB8116165B-50 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
MB8116165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
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