參數(shù)資料
型號(hào)： MB81V17800A-60L
廠商： Fujitsu Limited
英文描述： CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 2米× 8位快速頁(yè)面模式的DRAM的CMOS（2米× 8位快速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 19/25頁(yè)
文件大?。?/td> 520K
代理商： MB81V17800A-60L
19
MB81V17800A-60/60L/-70/70L
A
0
to A
10
CAS
V
IH
V
IL
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 13 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
HIGH-Z
ROW ADDRESS
t
RC
t
RAS
t
RP
t
RPC
t
RAH
t
ASR
t
CRP
t
CRP
t
OFF
t
OH
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row
addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched
on the falling edge of RAS. During RAS-only refresh, D
OUT
pins are kept in a high-impedance state.
CAS
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low
for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter
are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep-
aration for the next CAS-before-RAS refresh operation.
HIGH-Z
t
RC
t
RAS
t
RP
t
RPC
t
CHR
t
CSR
t
CPN
t
OFF
t
OH
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
相關(guān)PDF資料
PDF描述
MB81V17800A-70 CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V17800A-70L CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V17805A-60 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V17805A-60L CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V17805A-70 CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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