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參數(shù)資料
| 型號： | MB81V17800A-60L |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 2米× 8位快速頁面模式的DRAM的CMOS（2米× 8位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 520K |
| 代理商： | MB81V17800A-60L |
22
MB81V17800A-60/60L/-70/70L
CAS
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 17 – SELF REFRESH CYCLE (A
0
to A
10
= WE = OE = “H” or “L”)
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip
is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using
internal refresh address counter during “RAS = L” and “CAS = L”.
Exit from self refresh cycle is performed by togging RAS and CAS to “H” with specified t
CHS
min. In this time, RAS must be kept “H”
with specified t
RPS
min.
Using self refresh mode, data can be retained without external CAS signal during system is in standby.
Restriction for Self Refresh operation;
For self refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self Refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed
within t
REF
max.
2) In the case that burst CBR refresh or distributed burst RAS-only refresh are operated between read/write cycles
2,048 times of burst CBR refresh or 2,048 times of burst RAS-only refresh must be executed before and after
Self Refresh cycles.
HIGH-Z
t
OH
t
OFF
t
CPN
t
CSR
t
RASS
t
RPS
t
RPC
t
CHS
RAS
V
IH
V
IL
* Read/Write operation can be performed non refresh time within t
NS
or t
SN
Read/Write operation
Self Refresh operation
t
RASS
Read/Write operation
t
NS
< 2 ms
t
SN
< 2 ms
2,048 burst refresh cycle
2,048 burst refresh cycle
*
MB81V17800A-70/70L
Min
.
100
MB81V17800A-60/60L
Min.
100
Unit
Parameter
Max.
—
—
—
μ
s
No
.
Max.
—
—
—
100
101
102
Symbol
(At recommended operating conditions unless otherwise noted.)
RAS Precharge Time
CAS Hold Time
125
–50
ns
110
–50
RAS Pulse Width
ns
t
RASS
t
RPS
t
CHS
Note:
Assumes Self Refresh cycle only.
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
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