- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377886 > MB81V17800A-70 (Fujitsu Limited) CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | MB81V17800A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動(dòng)態(tài)RAM) |
| 中文描述： | 的CMOS 2米× 8位快速頁面模式的DRAM的CMOS（2米× 8位快速頁面存取模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 520K |
| 代理商： | MB81V17800A-70 |
5
MB81V17800A-60/60L/-70/70L
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix.
Since only eleven address bits (A
0
to A
10
) are available, the row and column inputs are separately strobed by
RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A
0
-through-A
10
and latched
with the row address strobe (RAS) then, ten column address bits are input and latched with the column address
strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS,
respectively. The address latches are of the flow-through type; thus, address information appearing after t
RAH
(min) + t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
to DQ
8
) is strobed by CAS and the setup/hold times are
referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE
goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-
enable signal.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of two TTL loads. Polarity of the output data is
identical to that of the input; the output buffers remain in the high-impedance state until the column address
strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the
following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
the falling edge of CAS when t
RCD
is greater than t
RCD
(max).
t
AA
:
from
column address input when t
RAD
is greater than t
RAD
(max).
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed,
the output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page
mode is implemented by keeping the same row address and strobing in successive column addresses. To
satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common.
For each fast page of memory, any of 1,024
×
8-bits can be accessed and, when multiple MB81V17800As are
used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be
addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
Parameter
Notes Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp.
Supply Voltage
*1
V
CC
3.0
3.3
3.6
V
0
°
C to + 70
°
C
V
SS
0
0
0
Input High Voltage, all inputs
*1
V
IH
2.0
—
V
CC
+0.3
V
Input Low Voltage, all inputs*
*1
V
IL
–3.0
—
0.8
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB81V17800A-70L | CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動(dòng)態(tài)RAM) |
| MB81V17805A-60 | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| MB81V17805A-60L | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| MB81V17805A-70 | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
| MB81V17805A-70L | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB82 | 功能描述:RECTIFIER BRIDGE 8A 200V BR-6 RoHS:否 類別:分離式半導(dǎo)體產(chǎn)品 >> 橋式整流器 系列:- 產(chǎn)品變化通告:Product Discontinuation 14/Mar/2011 標(biāo)準(zhǔn)包裝:1,500 系列:- 電壓 - 峰值反向(最大):1000V 電流 - DC 正向(If):1.5A 二極管類型:單相 速度:標(biāo)準(zhǔn)恢復(fù) >500ns，> 200mA（Io） 反向恢復(fù)時(shí)間(trr):- 安裝類型:表面貼裝 封裝/外殼:4-SMD 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:4-SDIP |
| MB820 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| MB-8210 | 制造商:Maxxtro 功能描述:Bulk |
| MB82101BAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB82101BBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。