參數(shù)資料
型號： MB81V17800A-70L
廠商： Fujitsu Limited
英文描述： CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 2米× 8位快速頁面模式的DRAM的CMOS（2米× 8位快速頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 9/25頁
文件大小： 520K
代理商： MB81V17800A-70L
9
MB81V17800A-60/60L/-70/70L
Notes:
*1.
Referenced to V
SS
.
I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open. I
CC
depends on the number of address change as RAS = V
IL
, CAS = V
IH
and V
IL
> –0.3 V.
I
CC1
, I
CC3
, I
CC4
and I
CC5
are specified at one time of address change during RAS = V
IL
and CAS = V
IH
. I
CC2
is specified during RAS = V
IH
and V
IL
> –0.3 V. I
CC6
is measured on condition that all address signals are
fixed steady state.
An initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only cycles
before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight
CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
AC characteristics assume t
T
= 5 ns.
Input voltage levels are 0V and 3.0V, and input reference levels are V
IH
(min) and V
IL
(max) for measuring
timing of input signals. Also, the transition time (t
T
) is measured between V
IH
(min) and V
IL
(max).
The output reference levels are V
OH
= 2.0 V and V
OL
= 0.8 V.
Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
is greater than the maximum recommended value
shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown. Refer to Fig.2
and 3.
If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
- t
CAC
-
t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
- t
CAC
-
t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
t
OFF
and t
OEZ
is specified that output buffer change to high-impedance state.
Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
t
RCD
(min) = t
RAH
(min) + 2 t
T
+ t
ASC
(min).
Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
Either t
RRH
or t
RCH
must be satisfied for a read cycle.
t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z state
through entire cycle.
Assumes that t
WCS
< t
WCS
(min).
Either t
DZC
or t
DZO
must be satisfied.
t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max).
Assumes that CAS-before-RAS refresh.
t
WCS
, t
CWD,
t
RWD,
t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristic only. If t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and D
OUT
pin
will maintain high-impedance state throughout the entire cycle. If t
CWD
≥
t
CWD
(min), t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and t
CPWD
≥
t
CPWD
(min), the cycle is a read-modify-write cycle and data from the selected
cell will appear at the D
OUT
pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle
and invalid data will appear the D
OUT
pin, and write operation can be executed by satisfying t
RWL
, t
CWL
, and t
RAL
specifications.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
*11.
*12.
*13.
*14.
*15.
*16.
*17.
*18.
*19.
*20.
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