參數(shù)資料
型號: MB81V17805A-70
廠商: Fujitsu Limited
英文描述: CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 200萬× 8位超頁模式動態(tài)RAM的CMOS(200萬× 8位超級頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 9/30頁
文件大小: 604K
代理商: MB81V17805A-70
9
MB81V17805A-60/-60L/-70/-70L
(Continued)
No.
Parameter
Notes
Symbol
MB81V17805A-60/
60L
Min.
MB81V17805A-70/
70L
Min.
Unit
Max.
Max.
31
Read Command Hold Time
Referenced to RAS
Read Command Hold Time
Referenced to CAS
Write Command Set Up Time
Write Command Hold Time
Write Hold Time from RAS
WE Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Set Up Time
DIN Hold Time
Data Hold Time from RAS
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay
Time
RAS Precharge Time to CAS
Active Time (Refresh Cycles)
CAS Set Up Time for CAS-before-
RAS Refresh
CAS Hold Time for CAS-before-
RAS Refresh
Access Time from OE
Output Buffer Turn Off Delay
from OE
OE to RAS Lead Time for Valid Data
OE to CAS Lead Time
OE Hold Time Referenced to
WE
OE to Data in Delay Time
RAS to Data in Delay Time
CAS to Data in Delay Time
DIN to CAS Delay Time
DIN to OE Delay Time
OE Precharge Time
*14
t
RRH
0
0
ns
32
*14
t
RCH
0
0
ns
33
34
35
36
37
38
39
40
41
42
43
*15,20
t
WCS
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RWD
t
CWD
0
10
24
10
15
10
0
10
24
77
32
0
10
24
10
17
13
0
10
24
89
36
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*20
*20
44
*20
t
AWD
47
54
ns
45
t
RPC
5
5
ns
46
t
CSR
0
0
ns
47
t
CHR
10
12
ns
48
*9
t
OEA
15
17
ns
49
*10
t
OEZ
15
17
ns
50
51
t
OEL
t
COL
10
5
10
5
ns
ns
52
*16
t
OEH
5
5
ns
53
54
55
56
57
58
t
OED
t
RDD
t
CDD
t
DZC
t
DZO
t
OEP
15
15
15
0
0
8
17
17
17
0
0
8
ns
ns
ns
ns
ns
ns
*17
*17
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